Method of controlling data reading capable of increasing...

Details Method of controlling data reading capable of increasing... Method of controlling data reading capable of increasing...

2005-01-25

2005-01-25

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030

Reexamination Certificate

active

06847580

ABSTRACT:
A method for controlling reading data that can increase the data transfer rate in an SDRAM of a posted CAS standard. A memory cell array is constituted by two sub-arrays that can be independently activated. When a READ command is received as an input one clock cycle after the input of an ACTV command, a row decoder activates only the sub-array containing the memory cell that is selected by a row address AX and column address AY, and then carries out the operations for reading data. The present invention thus reduces the areas that must be activated, thereby decreasing the load on the power supply and, when amplifying bit lines, shortening the time for the voltage of bit lines to attain the stipulated voltage. Consequently, the present invention increases the speed of reading data.

REFERENCES:
patent: 6067257 (2000-05-01), Kitsukawa et al.
patent: 6388937 (2002-05-01), Takeyama et al.

Affiliated with

Also associated with

Rating

Method of controlling data reading capable of increasing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of controlling data reading capable of increasing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlling data reading capable of increasing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3394567