Method of controlling a shared memory bus in a multiprocessor sy

Details Method of controlling a shared memory bus in a multiprocessor sy Method of controlling a shared memory bus in a multiprocessor sy

1990-06-29

1993-04-13

Dixon, Joseph L.

Boots, shoes, and leggings

395275, 395550, 364DIG1, G06F 1300, G06F 13376

Patent

active

052029735

ABSTRACT:
A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.

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