Method of contacting silicide tracks

Fishing – trapping – and vermin destroying

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Details

437193, 437228, 148DIG19, H01L 21283

Patent

active

050810650

ABSTRACT:
Disclosed is a method of contacting a metal silicide pattern on an integrated semiconductor circuit which is provided with a planarized dielectric layer. A silicide-forming metal layer (9), preferably a titanium layer, is provided on the surface of a silicon substrate having a field oxide patter (2) which is provided with a conductor pattern (4) of silicon. A layer (10) of amorphous (a-) silicon is provided locally on this metal layer to form "straps". The entire device is heated in a nitrogen-containing atmosphere, by which the metal layer (9) is converted at least partly into metal silicide (12). A dielectric layer (13), for example of silicon oxide, is provided over the entire surface. The layer (13) is planarized and provided with contact windows (15) on the metal silicide by etching, after which a metallization (16) is provided. According to the invention, the amorphous silicon layer is provided not only at the locations of the "straps", but also under at least those contact windows which are situated above the silicon pattern (4), and preferably below all contact windows, so that a thicker silicide layer (12B) is realized below these windows and partial or substantial removal by etching of the metal silicide in the "shallow" contact windows is prevented.

REFERENCES:
patent: 4708767 (1987-11-01), Bril
patent: 4873204 (1989-10-01), Wong et al.
van Houtum, H. J. W. et al., "TiSi.sub.2 Strap Formation . . . ," J. Vac. Sci. Technol. B6(6), Nov./Dec. 1988, pp. 1734-1739.
Fukumoto, M. et al., "Titanium Silicide Interconnect . . . ," IEEE Trans. Elec. Dev., vol. 35, No. 12, Dec. 1988, pp. 2328-2332.
Iyer, S. et al., J. Electrochem. Soc., vol. 132, No. 9, Sep. 1985, pp. 2240-2245.
Alperin, M. E., IEEE J. Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 61-69.

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