Method of constructing CMOS vertically modulated wells (VMW) by

Details Method of constructing CMOS vertically modulated wells (VMW) by Method of constructing CMOS vertically modulated wells (VMW) by

1994-11-22

1996-03-26

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437154, 437931, H01L 218238

Patent

active

055019935

ABSTRACT:
CMOS vertically modulated wells are constructed by using clustered MeV ion implantation to form a structure having a buried implanted layer for laterial isolation.

REFERENCES:
patent: 4710477 (1987-12-01), Chen
patent: 5160996 (1992-11-01), Odanaka
patent: 5384279 (1995-01-01), Stolmeijer et al.
Diffusion/Implantation, Dec. 1993 "MeV Implantation Technology Next-generation manufacturing with current-generation equipment" John Ogawa Borland, Ron Koelsch. brochure pp. 1-8.
Fowler, "MosFet Devices with high-gate dielectric integrity", IBM TDB, vol. 17, No. 1, Jun. 1974.

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