Method of configuring a process to obtain a thin layer with...

Details Method of configuring a process to obtain a thin layer with... Method of configuring a process to obtain a thin layer with...

2006-01-10

2009-02-03

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S464000

Reexamination Certificate

active

07485545

ABSTRACT:
A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined finishing sequence of operations that improve the surface quality of the layer. The minimum thickness is determined such that the density of through holes remains below the target maximum density after each operation in the finishing sequence.

REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 6100166 (2000-08-01), Sakaguchi et al.
patent: 6403450 (2002-06-01), Maleville et al.
patent: 6902988 (2005-06-01), Barge et al.
patent: 2002/0061660 (2002-05-01), Ito
patent: 2002/0106870 (2002-08-01), Henley et al.
patent: 2004/0115905 (2004-06-01), Barge et al.
patent: 2004/0151483 (2004-08-01), Neyret et al.
patent: 2004/0161948 (2004-08-01), Maleville et al.
patent: 2004/0166650 (2004-08-01), Yokokawa et al.
patent: 2004/0219370 (2004-11-01), Aga et al.
patent: 2004/0248380 (2004-12-01), Aulnette et al.
patent: 2005/0014346 (2005-01-01), Mitani et al.
patent: 2005/0148163 (2005-07-01), Nguyen et al.
patent: 2007/0287273 (2007-12-01), Boussagol et al.
patent: 2008/0038564 (2008-02-01), Bruel
patent: 1 193 749 (2002-04-01), None
patent: 2 797 713 (2001-02-01), None
patent: WO 03/009366 (2003-01-01), None
patent: WO 2004/079801 (2004-03-01), None
patent: WO 2005/013318 (2005-02-01), None
patent: WO 2005/043615 (2005-05-01), None
Celler, G.K. et al., “Frontiers of Silicon-on-Insulator”, J. Appl. Phys. vol. 93, No. 9, 2003, pp. 4955-4978.
Tong, Q.Y. et al., “Semiconductor Wafer Bonding: Sciences and Technology”, Wiley/Interscience technology publications, 1999.
Colinge, Jean-Pierre, Silicon-On-Insulator Technology: Materials to VLSI, 2ndEdition, Kluwer Academic Publishers, 1997, pp. 50-51.
Aspar et al., “Smart-Cut: An Original Way to Obtain Thin Films by Ion Implantation,” Conference on Ion Implantation Technology, Sep. 17-22, 2000, pp. 255-260.
Auberton-Herve et al., “Smart-Cut: The Basic Fabrication Process for Unibond SOI Wafers,” IEICE Transactions on Electronics, vol. E80-C, No. 3, pp. 358-363 (1997).
Search Report dated Aug. 10, 2005 from International application No. PCT/IB2004/004390.

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