Boots – shoes – and leggings
Patent
1989-12-08
1990-12-11
Shaw, Dale M.
Boots, shoes, and leggings
364745, G06F 738
Patent
active
049775359
ABSTRACT:
Floating point numbers are processed by an apparatus, where an increment step may be necessary on a number but where that number may or may not have to be normalized, depending on the computation. The invention is particularly useful in rounding after multiplying, as well as in exponent incrementing after adding. The apparatus also detects a uniform bit state in a number, e.g. detecting all zeroes, such as for overflow detection in a floating point multiplier. A first number and a second number comprising the first number incremented by one or two are computed substantially simultaneously. In one use, one of the first and second numbers is selected in accordance with the outcome of a further predetermined computation. In another use, the most significant bits of the numbers are compared and it is determined that all the bits of the first number are equal if, and only if, the most significant bits are unequal.
REFERENCES:
patent: 4528640 (1985-07-01), Criswell
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4719589 (1988-01-01), Tanaka
patent: 4796217 (1989-01-01), Takahashi et al.
"64 Bit Monolithic Floating Point Processors", Frederick A. Ware, et al., IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct., 1982, pp. 898-907.
King Robert L.
Mai Tan V.
Motorola Inc.
Shaw Dale M.
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