Method of compressing data for use in performing VLSI mask layou

Details Method of compressing data for use in performing VLSI mask layou Method of compressing data for use in performing VLSI mask layou

1995-10-19

1997-03-18

Teska, Kevin J.

Boots, shoes, and leggings

3642606, 3642604, 3642756, 364DIG1, G06F 1750

Patent

active

056131020

ABSTRACT:
A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.

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patent: 5299139 (1994-03-01), Baisuck et al.
patent: 5325476 (1994-06-01), Takii et al.
K. W. Chiang, et al. "Time-Efficient VLSI Art-Work Analysis Algorithms in GOALIE2", IEEE Transactions on CAD, vol. 81 No. 5, pp. 640-647, Jun. 1989.
T. Szymanski, et al. Special Feature: "Goalie: A Space Efficient System for VLSI Artwork Analysis", IEEE Design of Test, pp. 64-72, Jun., 1985.

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