Method of compacting layouts of semiconductor integrated circuit

Details Method of compacting layouts of semiconductor integrated circuit Method of compacting layouts of semiconductor integrated circuit

1995-03-29

1997-09-02

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, G06F 1750

Patent

active

056638922

ABSTRACT:
A method for performing compaction of a layout of a semiconductor integrated circuit designed in a hierarchy is described. The compaction of the layout is carried out by repeating a single level compaction process for compacting cell layouts in one of the hierarchical levels from a lowest level to a highest level of the hierarchical levels. The single level compaction process comprises a first replacement step of replacing lower level cell layouts in a current level cell layout with abstract cell layouts having the same profile and the same positions of terminals to be connected to the current level cell layout as the lower level cell layouts have in advance of compaction. The compaction of the current level cell is performed under a constraint that the relocations of the terminals of the current level cell layout after compaction from the original positions before compaction are possible within prescribed ranges. After compaction, the abstract cell layouts is replaced by the lower level cell layouts.

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