Method of combining lower order and translated upper order bits

Details Method of combining lower order and translated upper order bits Method of combining lower order and translated upper order bits

1990-07-19

1993-10-12

Lee, Thomas C.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395425, 36523001, 36523006, 3649556, 3649564, 3649658, 3649705, 36424531, 3642469, 3642558, 364256, 364DIG1, G06F 1200, G06F 1202, G06F 1206

Patent

active

052533506

ABSTRACT:
In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.

REFERENCES:
patent: 4407016 (1983-09-01), Bayliss et al.
patent: 4774652 (1988-09-01), Dhuey et al.
patent: 4849875 (1989-07-01), Fairman et al.
patent: 4868738 (1989-09-01), Kish et al.
patent: 5109521 (1992-04-01), Culley

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