Method of combining gate array and standard cell circuits on a c

Details Method of combining gate array and standard cell circuits on a c Method of combining gate array and standard cell circuits on a c

1988-03-18

1991-09-24

Lall, Parshotam S.

Boots, shoes, and leggings

364488, 437 56, 437 74, 357 42, 357 45, 357 47, 357 52, H01L 2170, G06F 1560

Patent

active

050519174

ABSTRACT:
A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

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