Method of combining gate array and standard cell circuits on a c

Details Method of combining gate array and standard cell circuits on a c Method of combining gate array and standard cell circuits on a c

1987-02-24

1988-11-22

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 8, 437 74, 437141, H01L 2138

Patent

active

047866136

ABSTRACT:
A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum ground rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguosuly arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing the chips density and performance versus hardware turn-around-time.

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