Method of combining gate array and standard cell circuits on a c

Details Method of combining gate array and standard cell circuits on a c Method of combining gate array and standard cell circuits on a c

1991-03-28

1994-11-29

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, 327565, H03K 19177

Patent

active

053695950

ABSTRACT:
A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

REFERENCES:
patent: 4412237 (1083-10-01), Matsummura et al.
patent: 4513307 (1985-04-01), Brown
patent: 4523106 (1985-06-01), Tanizawa et al.
patent: 4562453 (1985-12-01), Noguchi et al.
patent: 4570176 (1986-02-01), Kolwicz
patent: 4589007 (1986-05-01), Kuboki et al.
patent: 4633571 (1987-01-01), Kolwicz
"A Software Environment for Building Core-Microcomputer Compilers" T. G. Matheson et al., International Conference on Computer Design, pp. 221-224, Oct. 7-10, 1985.
"Configurable 6845 Megacell Incorporated With 2UM CMOS Gate Array" K. Pierce et al, IEEE 1986 Custom Integrated Circuits Conference, pp. 565-567.
"HAPPI: A Chip Compiler Based on Double-Level-Metal Technology," R. Putatunda et al., 23rd Design Automation Conference, Paper 41.4, pp. 736-743, 1986.
"Philo-A VLSI Design System," R. Donze et al., Design Automation Conference, Las Vegas, Nev., Jun. 1982, pp. 163-169.
"Programming Language Makes Silicon Compilation a Tailored Affair," M. R. Burich, Electronic Design, Dec. 12, 1985, pp. 135-142.
"Structured Arrays-A New ASIC Concept Provides the Best of Gate Arrays and Cell Based Custom," R. Walker et al., IEEE 1985 Custom Integrated Circuits Conference, pp. 252-257.

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