Method of coherent demodulation for phase shift keying and a dev

Pulse or digital communications – Repeaters – Testing

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375 94, 375118, 329307, H03D 322, H04L 2722

Patent

active

053373316

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention concerns a method of coherent demodulation for phase shift keying and a device for implementing the method.
The invention is thus applicable to transmission systems using type PSK2 or PSK4 modulation for example.
In a current demodulator known in the art, the analog signal at the intermediate frequency f.sub.i is transformed to the base band by multiplication in in-phase and quadrature channels, followed by filtering to remove image frequencies. The signal is then digitized for each channel and, after passing through a matched filter, a baseband signal is obtained, which may be represented by a complex number: +n.sub.k ##EQU1## s.sub.k being the symbol transmitted at the instant kT.sub.s ; M representing the number of phase states and 1 being an integer corresponding to the coded bit or bits; kT.sub.s ; difference between the transmission and reception oscillators.
If .delta.w=.DELTA.w.sub.i T.sub.s we have: notation:
In demodulation based on channel estimation, the essential condition for good operation is the insertion of R reference symbols (known a priori to the receiver) every I information symbols, so as to form blocks of R+I symbols. The R reference symbols may be identical for each block or equally be constructed on the basis of one (for PSK2) or two (for PSK4) pseudorandom sequences of period N=2.sup.m -1, such that m>>R. The order of magnitude of R may be around ten and that of I of some tens.
If the channel is slowly varying it can be assumed that .phi..sub.k =.phi. and .delta.w.apprxeq.0, so that in fixing the origin of time for the start of each block we take:
Thanks to the knowledge of the signal received in the interval [0, . . . R-1] and from the Gaussian nature of the additive noise n.sub.k, the variable h can be estimated from the maximum likelihood. This means minimizing a function L defined as follows: ##EQU2##
We can then calculate the gradient of L relative to h.sub.r and h.sub.i, with the notation h=h.sub.r +jh.sub.i : ##EQU3##
Setting G.sub.hr (L)+jG.sub.hi (L) to zero we obtain: ##EQU4##
To effect the coherent demodulation we then perform: ##EQU5## The demodulation should preserve the power of the received signal; hence the normalization by .vertline.h.vertline..
The advantage of this method of demodulation is the removal of the phase ambiguity, as well as its good resistance to Gaussian noise. It can also be noted that, once the symbol synchronization is acquired, the convergence of the phase estimator is less than the duration of a block, namely (R+I)T.sub.s iterations. The low frequency of the phase estimation makes the method inapplicable when: ##EQU6##
This means a major constraint on the drift of the oscillators.
In loop demodulation, the gradient algorithm is used to minimize an estimation function as described in the article entitled "Simultaneous adaptive estimation and decision algorithm for carrier modulation data transmission systems" by H. Kobayashi, (IEEE Transaction and communication technology; vol COM-19, June 1971, pages 268-280). This estimation function is worked out in order to obtain a decision criterion according to the maximum likelihood.
In deriving this estimation function an estimate of the phase error is obtained: =ow.sub.k-1 -.alpha.e.sub.k mod2.pi. .alpha. is also a loop parameter. It may be so chosen that .alpha.=.beta..sup.2 /2.
This decision-based system does not resolve the problem of phase ambiguity. Its convergence is relatively slow when noise is significant.


SUMMARY OF THE INVENTION

The object of the invention is to resolve these problems.
To this end the present invention proposes a method of coherent demodulation for phase shift keying includes: transmitted at the start of each block of data:
It likewise proposes a device for implementing this method, including:
The phase estimation circuit advantageously comprises in succession: of the delay circuit passed through a multiplier circuit, an adder-accumulator circuit and a conversion circuit:
This circuit further includes: inputs of the multip

REFERENCES:
patent: 4246654 (1981-01-01), Malm
patent: 4599732 (1986-07-01), LeFever
patent: 5049830 (1991-09-01), Yoshida
patent: 5128626 (1992-07-01), Iwasaki
patent: 5208886 (1993-05-01), Edbauer

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