Method of coding a number for storing in a memory

Details Method of coding a number for storing in a memory Method of coding a number for storing in a memory

1997-08-29

2001-09-25

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from mixed base codes

C341S057000

Reexamination Certificate

active

06295011

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an implementation of a digital signal processor (DSP) architecture for use as a digital interpolation filter or a digital decimation filter.
2. Discussion of Related Technology
Commonly utilized DSP architecture for digital interpolation or digital decimation filters employ bit multiplication schemes that require hardware to perform a series of shifts and adds to multiply data by a particular filter coefficient. This typically requires the use of an adder for each group of bits to be multiplied where the number of adders is greater than one half the number of bits of the filter coefficient to be multiplied.
These commonly utilized filter also typically do not include a common data path for multiplication scaling of the numbers to be multiplied and accumulation of the products.
SUMMARY OF INVENTION
Described herein is a novel implementation of a DSP architecture which can be used to implement a digital interpolation filter, or a digital decimation filter, depending on the design requirement, and a method of performing such interpolation or decimation of a multi-bit input signal. The present invention codes a number, preferably a filter coefficient, performs scaling and multiplication functions upon the coded number and then decodes the product. This method results in a reduced requirement for adders, such that the number of required addition operations is equal to one half the number of bits representing the known number to be multiplied, typically bits of a filter coefficient, by another number, typically the input data.
The present invention utilizes a common data path for multiplication scaling of the numbers to be multiplied and accumulation of the products. This greatly reduces the amount of required hardware to perform the DSP filter multiplications.


REFERENCES:
patent: 5448509 (1995-09-01), Lee et al.
patent: 5764558 (1998-06-01), Pearson et al.
Wei et al, “Signed Binary Delta Modulation Digital Filter,” IEEE, Entire Document, 1988.*
Wong, “Fully Sigma Delta Modulation Encoded FIR Filters,” IEEE, Entire Document, 1992.*
Hashemian, “A New Number System for Faster Multiplication,” IEEE, p. 682, 1997.*
Do et al, “Efficient Filter Design for IS-95 CDMA Systems,” IEEE, p. 1013, Aug. 1996.

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