Method of chemically mechanically polishing an electronic compon

Details Method of chemically mechanically polishing an electronic compon Method of chemically mechanically polishing an electronic compon

1996-07-25

1998-08-18

Dentz, Bernard

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 89, H01L 2102

Patent

active

057958262

ABSTRACT:
A method of forming interlevel studs of at least two different materials in an insulating layer on a semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias are formed through the BPSG layer in array areas. A thin doped poly layer is deposited on the surface of the BPSG layer. The structure is annealed and vias are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.

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Anonymous, "Electrical Contacts through Planar Isolation" Research Disclosure, Jul. 1990 #315, Kenneth Mason Publications, Ltd. England.
"Fully-Planarized Double-Poly Self-Aligned Bipolar Transistor with Self-Aligned Chem-Mech Polished Emitter-and Collector-Contact" IBM Technical Disclosure Bulletin, vol. 35, No. 4A, pp. 197-199, Sep. 1992.

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