Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-09-06
2002-10-22
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C156S345420, C216S038000, C216S088000, C216S089000, C438S693000, C438S745000
Reexamination Certificate
active
06468911
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-254565, filed Sep. 8, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to a method of manufacturing a semiconductor device and more particularly to methods of chemical/mechanical polishing of the surface of a semiconductor device.
The chemical/mechanical polishing (CMP) has been used for planarization of interlayer insulating films, metal interconnections, polysilicon filling device isolation trenches, etc.
In planarizing polysilicon by CMP, a stopper film consisting of silicon dioxide or nitride silicon is used in order to stop the progress of polishing after planarization. In this case, it is required to polish polysilicon selectively in comparison with the stopper film.
In the CMP, however, polishing/etching is performed based on the combined action of the chemical action of a polishing slurry and the mechanical action of abrasive grains. Depending on selected polishing conditions, therefore, “dishing” may occur. The “dishing” means that a recess
102
is formed, as shown in
FIG. 1
, on top of polysilicon
101
that fills a trench
100
after polishing. The occurrence of the “dishing” causes a degradation in the device performance, a reduction in the device yield, and a decrease in the device reliability.
In particular, the “dishing” remarkably occurs in wide trenches when trenches of different widths are simultaneously filled with polysilicon (at a rate more than twenty times that for narrow trenches). It is thought that the dishing occurs due to deformation of a polishing pad and a difference in polishing rate between polysilicon and stopper film. An improvement can be made through the use of a polishing pad of high elastic modulus and a fixed abrasive grain type of grinding stone.
However, since the polishing pad of high elastic modulus and the fixed abrasive grain type of grinding stone are stiff, it is known that a load is concentrated on a portion of abrasive grains at CMP time and consequently scratching becomes easy to occur on the polished surface of a semiconductor device. The “scratching” means that the polished surface
103
of the semiconductor device gets scratches
104
as shown in FIG.
2
. As is the case with the “dishing”, the occurrence of the “scratching” causes a degradation in the device performance, a reduction in the device yield, and a decrease in the device reliability.
It is said that the stiff polishing pad is not suited for polishing semiconductor devices because it, while being capable of suppressing the dishing, makes the scratching easy to occur.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device chemical/mechanical polishing method which permits the dishing to be controlled while keeping the scratches from increasing.
To attain the object, according to an aspect of the present invention there is provided a chemical/mechanical polishing method of polishing the surface of a semiconductor device comprising the steps of: supplying a polishing pad with a slurry that contains a solvent, abrasive grains, and an additive for making viscosity variable so that the top portion of the polishing pad is soaked with the slurry; supplying the polishing pad with a viscosity modifier for increasing the viscosity of the slurry and hardening the top portion of the polishing pad soaked with the slurry to a given level of hardness; and polishing the surface of the semiconductor device with the slurry having its viscosity increased and the polishing pad having its top portion hardened.
According to another aspect of the present invention there is provided a chemical/mechanical polishing method of polishing the surface of a semiconductor device comprising: a first step of supplying a polishing pad with a slurry that contains a solvent, abrasive grains, and an additive for making viscosity variable so that the top portion of the polishing pad is soaked with the slurry; a second step of, after the first step, polishing the surface of the semiconductor device with the top portion of the polishing pad soaked with the slurry; a third step of supplying the polishing pad with a viscosity modifier for increasing the viscosity of the slurry and hardening the top portion of the polishing pad soaked with the slurry to a given level of hardness; and a fourth step of, after the third step, polishing the surface of the semiconductor device with the slurry having its viscosity increased and the polishing pad having its top portion hardened.
According to the chemical/mechanical polishing methods, since the to-be-polished surface of the semiconductor device is polished with the hardened top portion of the polishing pad, the polishing pad is difficult to deform and hence the dishing is controlled.
In addition, since the to-be-polished surface of the semiconductor device is polished with the slurry with increased viscosity, the polishing pad slips on a layer of slurry after the surface has been flattened and has difficulty contacting with the polished surface. Thus, the progress of the chemical/mechanical polishing is impeded after the polished surface has been flattened and consequently the dishing is controlled.
Moreover, since the progress of the chemical/mechanical polishing is impeded after the polished surface has been flattened, the scratches produced on the polished surface is kept from increasing.
Furthermore, the viscosity of the slurry is increased on the polishing pad by supplying the polishing pad with the viscosity modifier. Thus, the top portion of the polishing pad can be hardened in a state where it is deformed to conform to a warp in the polished surface of the semiconductor device, which allows an improvement in global flatness.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 6046111 (2000-04-01), Robinson
patent: 6224464 (2001-05-01), Nojo et al.
patent: 10-242090 (1988-09-01), None
patent: 8-22970 (1996-01-01), None
patent: 11-251276 (1999-09-01), None
Nishioka et al., “Modeling on Hydrodynamic Effects of Pad Surface Roughness in CMP Process,” Proceedings of the 1999 (May 24-26, 1999), pp. IITC99-89-99-91.
Miyashita Naoto
Nishioka Takeshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Powell William A.
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