Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-06-28
2003-05-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06569694
ABSTRACT:
FIELD OF INVENTION
The present invention relates to integrated circuit packaging technology, and more specifically, to a computerized procedure for checking a Ball Grid Array (BGA) substrate design.
BACKGROUND ART
The explosive growth of high-density packaging has created a tremendous impact on the electronic assembly and manufacturing industry. Ball grid array (BGA), chip-scale package (CSP), and solder-bumped flip chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies.
In particular, BGA packages give designers the capability to put more functionality into a small area. BGA packages provide a smaller footprint on the circuit board, albeit requiring the higher level of technology on the circuit board for a similar density in lines/spaces and small vias. As schematically illustrated in
FIG. 1
, a BGA package uses solder balls arranged in a grid pattern for connecting the package to a printed circuit board. In accordance with conventional practice, the BGA package is attached to the circuit board by reflowing the solder balls to make connections to conductors or trace metal patterns at the surface of the printed circuit board.
An integrated circuit (IC) chip or die is mounted on a substrate that contains plated via holes and the solder balls on its underside. The die has bond pads that are connected by bond wires to bond fingers on the upper surface of the substrate. A conventional integrated circuit encapsulant, such as a plastic molding compound, an epoxy resin or a potting compound is used to protect the chip and the wire interconnects. The packaged integrated circuit is bonded to the printed circuit board by reflowing the solder balls, typically at a temperature up to about 250° C.
As BGA packages occupy small areas on the circuit board, they found measurable success in small consumer oriented electronics, such as laptop computers, pagers and cellular phones.
BGA substrates are designed using various computer-aided design (CAD) tools such as Cadence® Advanced Package Design (APD) software. Then, BGA substrate manufacturers send BGA substrate designs to BGA package manufacturers for checking. Conventionally, a BGA substrate design is checked manually to make sure that the substrate design complies with the BGA package specification. Such checking procedures are time-consuming and result in multiple errors.
Therefore, it would be desirable to develop a computerized procedure for checking BGA substrate design.
SUMMARY OF THE INVENTION
The present invention offers a novel method of checking a substrate design made using a computer-aided design (CAD) tool. The method involves entering into an interface software system interfaced to the CAD tool, a user's netlist representing a die to be mounted on the substrate being checked. The interface system automatically extracts a design netlist representing the substrate being checked, and compares the design netlist to the user's netlist. If no differences are found, the substrate design is considered to be proper.
In accordance with a preferred embodiment of the present invention, the substrate being checked may be a ball grid array substrate. The CAD tool may be an advanced package design (APD) tool.
The user's netlist may comprise identification numbers and coordinates of die pads, and netnames representing functions of the die pads. The design netlist may comprise identification numbers and coordinates of die pads, netnames representing functions of the die pads, identification numbers and coordinates of bond fingers, and identification numbers and coordinates of solder balls.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5353234 (1994-10-01), Takigami
patent: 5551014 (1996-08-01), Yoshida et al.
patent: 6245599 (2001-06-01), Goto et al.
patent: 6429029 (2002-08-01), Eldridge et al.
Sarma Pranabendra
Tain Alexander
Vivares Valerie
Advanced Micro Devices , Inc.
Hoang Quoc
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