Method of checking alignment accuracy of patterns on stacked...

Image analysis – Applications – Manufacturing or product inspection

Reexamination Certificate

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Reexamination Certificate

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07136520

ABSTRACT:
A method of checking overlap accuracy of patterns on fourth semiconductor layers. The first checking pattern is formed on the first semiconductor layer, the second checking pattern is formed on the second semiconductor layer, the third checking pattern is formed on the third semiconductor layer and the fourth checking pattern is formed on the fourth semiconductor layer. The first, second and third checking patterns overlap to form the first rectangular frame and the fourth checking pattern is surrounded by the first rectangular frame. A first pair of parallel sides of the first rectangular frame is formed by the first checking pattern and the second pair of parallel sides of the first rectangular frame is formed by the second and third checking patterns. Overlap accuracy of the patterns is obtained by checking the location error between the fourth checking pattern and the first checking pattern and the location error between the fourth checking pattern and the second and third checking patterns respectively.

REFERENCES:
patent: 4593406 (1986-06-01), Stone
patent: 5109430 (1992-04-01), Nishihara et al.
patent: 5189707 (1993-02-01), Suzuki et al.
patent: 5308682 (1994-05-01), Morikawa
patent: 6327513 (2001-12-01), Ziger

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