Electricity: measuring and testing – Plural – automatically sequential tests
Patent
1985-03-28
1987-10-06
Strecker, Gerard R.
Electricity: measuring and testing
Plural, automatically sequential tests
324158T, 324158D, 324158R, 250310, 250311, G01R 3128, G01N 2300
Patent
active
046985875
ABSTRACT:
A method for characterizing critical timing paths and analyzing timing related failure modes in high clock rate photocurrent at the drain of a single transistor in a very large scale integrated circuit. The laser testing apparatus utilized with the method of this invention incorporates therein a laser having its output beam focused onto the drain junction of the transistor under test. The localized injection of electromagnetic radiation produces a photocurrent at the drain junction of the transistor at specific times during the testing procedure which increases the logic level transition times associated with that particular node. This causes an increase in the minimum operating power supply and/or a decrease in the maximum operating frequency at which the microcircuit will properly function. Consideration of these parameters and the level of photocurrent provide a measurement related to the worst case timing margin which occurs during the functional test of the integrated microcircuit.
REFERENCES:
patent: 2790952 (1957-04-01), Pietenpol
patent: 3461547 (1969-08-01), Di Curcio
patent: 3803413 (1974-04-01), Vanzetti et al.
patent: 3969670 (1976-07-01), Wu
patent: 4172228 (1979-10-01), Gauthier et al.
patent: 4182024 (1980-01-01), Cometta
patent: 4332833 (1982-06-01), Aspnes et al.
patent: 4380864 (1983-04-01), Das
patent: 4454585 (1984-06-01), Ele
patent: 4588950 (1986-05-01), Henley
patent: 4599558 (1986-07-01), Castellano, Jr. et al.
patent: 4642566 (1987-02-01), Fazekas
Pronobis, Mark T. et al, "Laser Die Probing for Complex CMOS," Proceedings of the International Symposium for Testing and Failure Analysis, Oct. 1982.
Shichman, Harold et al, "Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits," IEEE Journal of Solid State Circuits, Sep. 1968, pp. 285-289.
Henley, F. J., "Logic Failure Analysis of CMOS VLSI Using a Laser Probe", IEEE 22nd Annual Proceedings Reliability Physics, Apr. 3, 4, 5, 1984.
Burns Daniel J.
Eldering Charles A.
Pronobis Mark T.
Erlich Jacob N.
Nguyen Vinh P.
Singer Donald J.
Strecker Gerard R.
The United States of America as represented by the Secretary of
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