Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-18
2003-01-21
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260, C365S185330
Reexamination Certificate
active
06510085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to programmable semiconductor flash memory cells. More specifically, this invention relates to a method of programming short channel NOR flash memory cells using channel hot electrons. Even more specifically, this invention relates to methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during programming while maintaining fast programming speeds.
2. Discussion of the Related Art
One type of programmable memory cell is commonly referred to as a flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as the tunnel oxide layer.
Prior programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such programming operations, the source and p-well of the flash memory cell are maintained at or near ground level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can attain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation, and a relatively high programming current in the cell being programmed results. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of a flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate. As can be appreciated, the slower the rate of injection the longer the programming time to reach the desired threshold voltage.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell can be programmed by applying programming voltages as follows: a voltage, typically in the range of 8-10 volts to the control gate, a voltage in the range of 4 to 5.5 volts to the drain, grounding the source and grounding the substrate or p-well. As discussed above, these voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
In channel hot electron programming, hot electrons created by high lateral fields near the drain junction are injected into the floating gate. As discussed above, typical operating voltages for channel hot electron operation are: V
D
=4.0-5.5V, V
G
=8-10V, V
s
~0 V and V
sub
~0 V. One of the limitations of channel hot electron programming for short channel NOR flash memory arrays is that the unselected cells sharing the same bitline begin to leak current when the high drain voltage is applied to the bitline. This leakage current I
d
is due to the Dibl (drain induced barrier lowering) effect in short channel devices. The combination of a large leakage current from the unselected cells and a large programming current from the selected cell being programmed results in unacceptably high total programming currents during device programming operation.
Therefore, what is needed is a method of programming to reduce or eliminate the leakage current for the unselected cells without decreasing the programming speed of the selected bit being programmed.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during the programming and soft programming operations.
In accordance with a first aspect of the invention, during programming a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. In accordance with a second aspect of the invention, during soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, a voltage of between 4 and 5.5 volts is applied to the drains, a voltage of between 0.5 and 2 volts is applied to the sources and a voltage of between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells being soft programmed.
In accordance with another aspect of the invention, the selected voltages applied during programming and soft programming are determined during either computer modeling or an empirical precharacterization procedure.
The described invention thus provides methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during the programming and soft programming operations.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifi
Chang Chi
Fastow Richard
Haddad Sameer
Park Sheunghee
Wang Zhigang
Lam David
Nguyen Viet Q.
Wagner , Murabito & Hao LLP
LandOfFree
Method of channel hot electron programming for short channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of channel hot electron programming for short channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of channel hot electron programming for short channel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3071557