Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-02-01
2004-04-13
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000, C341S159000, C341S166000
Reexamination Certificate
active
06720895
ABSTRACT:
This invention pertains generally to digital electronics and more particularly to high-speed analog-to-digital converters.
BACKGROUND
Many electronic applications require conversion of analog signals into digital signals. This is done by sampling the instantaneous value of the analog signal periodically and then representing each of these instantaneous values in digital form. If the periodic sampling rate is at least twice the highest frequency present in the analog signal, no information is lost in the sampling, as taught by the Shannon theorem. An electronic device that accomplishes this sampling and converts the samples to digital form is known as an Analog-to-Digital Converter (ADC).
For example, a well-known application of the ADC is to record music on a compact disk (CD). Musical instruments produce analog (continuously varying) sounds. These sounds are converted into an analog electrical signal by a microphone. In turn this analog electrical signal may be converted into digital form by sampling it periodically and representing the value of each sample as a binary number. The value of such an analog signal at a first sampling time might be 0.01 volt, at the next sampling time 0.1 volts, and at the next sampling time 0.5 volts. Represented as binary numbers with 8-bit resolution, these values are 0000 0001, 0000 0110, and 0011 0010, respectively. The human ear cannot hear frequencies higher than about 20 kiloHertz (kHz), so if the analog musical signal is sampled with sufficient resolution at least twice that fast—40,000 samples per second—virtually all the perceptible information in the original signal will be faithfully preserved in the digital conversion. Commercial CDs are recorded with digital signals obtained at a slightly higher sampling rate of 44,000 samples per second.
As operating frequencies of electronic devices have grown higher and higher, there has developed a corresponding need for a way to convert analog signals into digital form at sampling rates of many millions of samples per second. This has posed numerous difficulties for circuit designers, especially in crafting small, low-power devices that can be implemented as integrated circuits (ICs).
One approach to implementing a small, low-power, high-speed ADC has been the “pipeline” architecture. In the simplest pipeline ADC, a sampled value of an analog input signal is applied to a first pipeline stage where it is compared with a reference voltage to generate the most significant bit (MSB) of the digital output signal. This bit is converted into an analog value that is subtracted from the sample value to provide a residue. The residue is amplified and applied to a second pipeline stage wherein the preceding process is repeated to generate the next MSB, and so on through each successive pipeline stage to the least significant bit (LSB). The gain of each amplifier stage must be exactly two in order to get an accurate binary digital representation of the analog input signal.
Karanicolas, Lee and Bacrania in “A 1-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC”,
IEEE Journal of Solid
-
State Circuits,
Vol. 28, No. 12, December 1993, propose an ADC having a pipeline architecture but with an amplifier stage gain of 1.93 rather than two. This ADC includes a simple radix conversion (error-correction) circuit to compensate for the gain of the amplifier stages being slightly less than two. This ADC offers a sampling rate of one million samples per second (MSa/s).
More recently, a pipeline ADC as disclosed by Carreira, Dupuy and Franca in “A Compact Three-Step Pipelined CMOS Current-Mode A/D Converter”,
IEEE International Symposium on Circuits and Systems,
1997, page 465, has achieved a sampling rate of 54 MSa/s. This device employs relatively complex multiple-bit flash converters in each pipeline stage.
An example of a high-speed ADC that employs a pipeline structure with single-bit converters in each pipeline stage is provided by Hughes, Mee and Donaldson in “A Low Voltage 8-Bit, 40 MS/S Switched-Current Pipeline Analog-to-Digital Converter”,
IEEE International Symposium on Circuits and Systems,
2001, page I-572. The device proposed by Hughes et al. achieves a maximum sampling rate of 40 MSa/s.
It is possible to design high-speed current amplifiers from which one could fabricate an ADC having a sampling rate in excess of 54 MSa/s. However, it has been difficult to operate such amplifiers at the desired switching speeds with low power, and it has been difficult to accurately fix the gain of such amplifiers during fabrication. Accordingly, there remains a need for a way to fabricate an ADC that can accurately convert an analog signal into a digital one, that can achieve sampling rates substantially higher than 54 MSa/s, and that can be economically implemented in a low-power circuit on a small IC.
SUMMARY OF THE INVENTION
The invention provides a method of using multiple linear regression analysis to calibrate a pipeline ADC having a plurality of amplifier stages each with gain less than two. Such an ADC calibrated in this manner operates at switching speeds more than twice as fast as speeds that have been achieved by other ADCs, uses very low power, and can be economically fabricated in a very small area of an integrated circuit.
In one aspect of the invention, an analog calibration signal is applied to an ADC to obtain a plurality of codes, multiple linear regression analysis is performed on the codes to generate a plurality of weighting factors, and these weighting factors are then stored for later use.
It may be desirable to use the weighting factors to calculate register values and then store these register values in a set of lookup tables. Optionally, register values for a most-significant-bits lookup table are calculated during the multiple linear regression analysis to reduce any harmonic distortion.
Higher-order terms may be generated during the multiple linear regression analysis and used to calculate harmonic distortion correction values. These values are then stored, for example in a post-processing lookup table, for use in reducing any harmonic distortion in the digital output signal.
A method of converting an analog input signal into a digital output signal according to another aspect of the invention includes applying an analog calibration signal to an ADC to obtain a plurality of codes, performing multiple linear regression analysis on the codes to generate a plurality of weighting factors, storing the weighting factors, applying the to-be-converted analog input signal to the ADC to obtain radix bits, and using the stored weighting factors to convert the radix bits into the digital output signal.
Storing the weighting factors may include calculating register values and storing these values in a set of lookup tables, and values in the lookup tables are then used to convert the radix bits into the digital output signal.
As described above, higher-order terms may be generated during the multiple linear regression analysis and used to calculate harmonic distortion correction values. These values are used to reduce any harmonic distortion in the digital output signal.
In another aspect, the invention provides an analog-to-digital converter having current-mode pipeline stages that provide a plurality of radix bits according to an analog input signal and a radix conversion circuit that converts the radix bits into a digital output signal according to a plurality of weighting factors derived by multiple linear regression analysis of a calibration signal.
In one instance, the radix conversion circuit includes a plurality of registers each of which receives one of the radix bits and provides a weighted signal in response, and an adder to add the weighted signals from the registers to provide the digital output signal.
The analog-to-digital converter may include a post-processing distortion correction circuit that applies a plurality of harmonic distortion correction values derived from higher-order terms generated during the multiple linear regression analysis of the calibration signal to reduce h
Holcomb Matthew S.
Kang James
Neff Robert M. R.
Poulton Kenneth D.
Agilent Technologie,s Inc.
Mai Lam T.
Schulze Herbert R.
Tokar Michael
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