Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2001-06-26
2003-06-24
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S099000, C705S029000
Reexamination Certificate
active
06584370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer implementable decision support systems for determining a production schedule of feasible material releases within a complex multi-stage manufacturing system architecture. In more particularity, the present invention relates to a system for rationing manufacturing resources among competing demands according to a defined set of business rules.
2. Background Description
The manufacturing of semiconductors is a complex and refined process. This process includes everything from growing silicon crystals, to the actual placement and soldering of chips to a printed circuit board. Initially, raw wafers are cut from a silicon ingot and processed through a specific sequence of work centers. The end goal of this process is to build a set of integrated circuits on the surface of the silicon wafer according to a specific circuit design. This process involves repeatedly applying four basic steps: deposition, photolithography, etching, and ion implantation. These steps are the means by which materials with specific dielectric properties (e.g., conductors, insulators) are deposited on the surface of the wafer according to the precise circuit design specifications. These steps are repeated many times to build up several layers (typically between 12 and 25 layers) of the circuits.
After the circuits have been built on the wafers they are tested to determine the resultant yield of operational circuits and tagged for later reference. The circuits are then diced and sorted, and subsequently wire bonded to a substrate to assemble a module. These modules, which are further tested to determine electromagnetic and thermal characteristics, are eventually combined on printed circuit boards to form cards. Finally, the cards are tested and those that pass are eventually used in the assembly of a wide range of finished electronic products (e.g., personal computers, printers, CD players, etc.). From the point of view of semiconductor manufacturing, the modules and cards are, mostly, the finished products taken to market.
To assemble the modules and cards (or other end products), a Bill of Material (BOM) is needed to specify the required components used in the assembly of each particular part number (PN) produced within the manufacturing system. The BOM can be used to generate a graphical representation of the stages within a manufacturing process for each of the finished products. For example,
FIG. 1
shows a high level block diagram of the BOM for semiconductor manufacturing which can be broken into the following four aggregate stages: wafer stage
110
, device/substrate stage
120
, module stage
130
, and card stage
140
. These aggregate stages may involve many steps each of which may significantly impact the flow of materials through the manufacturing system. For example, the wafer stage
110
may involve wafer fabrication involving many passes through photolithography work centers to build multiple levels of a circuit structure. The dicing of the silicon wafer stage
120
involves a single item in the production process which is then converted into different devices. Also, the card stage
140
may involve the assembly of many devices to generate a single card. These stages result in multiple qualities of items being output from various stages of the manufacturing system according to a known distribution.
Resource requirements at various stages in the manufacturing system play an important role in the development of a feasible production schedule in most industries. These resources are typically machines for carrying out the above mentioned processes in semiconductor manufacturing and may include items such as furnaces, cutting tools for dicing chips, and testing machines for determining the operational characteristics of devices. Typically, insufficient resources are available to accommodate perfect just-in-time processing at the various manufacturing stages for all orders. Thus, the finite availability of resources must be accounted for in computing a schedule, and in some cases processing must be carried out earlier or later than desired depending on such availability. A property of resource requirements which is typical in semiconductor manufacturing, but not common to most industries, is the fact that a component processed within the manufacturing system may have to revisit the same resource many times. This is referred to as reentrant flow scheduling.
In addition to the BOM, other sources of manufacturing information such as yields, cycle times, shipping routes, etc. are critical for advance planning and scheduling of the product. However, a fundamental problem faced in all manufacturing industries is the matching of demand and assets over a set time period. By way of example, production lead times necessitate the advance planning of production so that material releases throughout the production system are coordinated with the end customers demand for any of a wide range of finished products (typically on the order of thousands in semiconductor manufacturing). Such advance planning depends on the availability of finite resources which include, for example, finished goods inventory, work in process (WIP) at various stages of the manufacturing system and work center capacity. Furthermore, there may be multiple locations, processes, and work centers that may be utilized for a particular job.
As is known, product advance planning decisions are necessary due to the complicated process architecture and unavoidably long lead times to complete processing through all manufacturing stages for a finished product. For this reason and to accommodate the planning and scheduling functions within the semiconductor manufacturing industry, a tiered planning system was devised. The following is a summary based on the tier system devised by Sullivan, G. and Fordyce, K., 1990, “IBM Burlington's Logistics Management System”, Interfaces, 20, 1, 43-64. In this tiered system each tier is defined by the time frame to which the decisions pertains.
Tier 1: Long range (3 months to 7 yr) strategic level decisions such as mergers, capacity acquisition, major process changes, new product development, and long term policy based decisions.
Tier 2: Medium range (1 week to 6 months) tactical scheduling involving yield and cycle time estimation, forecasting and demand management, material release planning and maintenance scheduling.
Tier 3: Short to medium range (weekly planning) operational scheduling for optimizing consumption and allocation of resources and output of product, demand prioritization techniques, capacity reservation and inventory replenishment.
Tier 4: Short range (daily) dispatch scheduling for addressing issues such as machine setups, lot expiration, prioritizing of late lots, job sequencing, absorbing unplanned maintenance requirements and assigning personnel to machines.
The above taxonomy of planning and scheduling decisions is a hierarchical one, i.e., decisions in higher tiers affect lower tiers. For example, long range capacity acquisition decisions determine eventual yield and cycle times, the available resources that can be utilized, and the extent to which maintenance is to be scheduled in the future. As is known, decisions in higher tiers, by the nature of their long time frames, are made under considerable uncertainty and thus seek to anticipate future requirements based on current information. On the other hand, lower level tier decisions are of a corrective/reactive nature and act to absorb uncertainty not accounted for in the higher tiers. It is also noted that advanced production planning and scheduling decision support systems are typically run on a weekly basis; however, the planning horizon for such runs may range several years depending on the planning horizon of interest and the level of detail in forecasting. Thus, advance planning systems may impact decisions in tiers 1, 2 and 3 which, in turn, may affect tier 4 decisions. Therefore, the matching of assets to demand is a major plann
Denton Brian T.
Hegde Sanjay R.
Orzell Robert A.
Kolulak Richard
Lee Douglas S.
McGuireWoods LLP
Picard Leo
LandOfFree
Method of calculating low level codes for considering... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of calculating low level codes for considering..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of calculating low level codes for considering... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3128791