Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-08-29
2003-07-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S018000, C438S011000, C257S048000
Reexamination Certificate
active
06586264
ABSTRACT:
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a method of calculating characteristics of a semiconductor device formed on one surface of a semiconductor substrate having a gate electrode formed on part of an area of the surface and a program for conducting calculations to obtain the characteristics.
In the recent semiconductor devices, performance and integration are increasing in an amazing fashion. It is therefore desired to put new high-performance, low-priced semiconductor devices to the market. For this purpose, a simulation technique is used.
B) Description of the Related Art
Referring to
FIG. 9
, description will be given of a method of calculating characteristics of a semiconductor device in the prior art. In step ST
100
, gate lengths Lg(
1
) to Lg(N) of N semiconductor devices are respectively inputted to a simulator. These semiconductors are of the same configuration excepting that the gate length varies therebetween. In step ST
101
, one is assigned to the variable i. The variable i is used to identify one of the N semiconductor devices.
In step ST
102
, a process simulation is conducted for a semiconductor device having a gate length Lg(i). Concretely, such process conditions as an ion implantation condition and a thermal treatment condition are inputted to the simulator to calculate a distribution of impurity concentration in the semiconductor substrate. When the process simulation is finished, the processing goes to step ST
103
.
In step ST
103
, according to the impurity concentration distribution resultant from the process simulation, a current-voltage characteristic of the semiconductor device is calculated. This calculation is called “device simulation”. When the device simulation is completed, control goes to step ST
104
.
In step ST
104
, the variable i is incrementally increased by one. In step ST
105
, the variable i is compared with the number N of the semiconductor devices. If a condition i≦N is satisfied as a result, control returns to step ST
102
to execute the process simulation and the device simulation for the semiconductor devices having gate lengths for which the calculation has not been conducted. If the condition i>N is satisfied, the simulation processing is terminated.
In the calculation method of
FIG. 9
, the process and device simulations are executed for all semiconductor devices for which the calculation is to be conducted. However, since the process simulation takes a long period of time, when the process simulation is repeatedly conducted N times, the overall calculation time becomes quite long.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a calculation method and a program thereof which can reduce the calculation time required to calculate characteristics of a semiconductor device.
According to one aspect of the present invention, there is provided a method of calculating characteristics of a semiconductor device, comprising the steps of determining a gate length of a semiconductor device including a gate electrode on or above a partial area of a surface of a semiconductor substrate and setting the gate length determined as an upper-limit gate length, determining an impurity implantation condition for a semiconductor device of which a gate length is substantially equal to said upper-limit gate length and calculating a representative impurity concentration distribution of the semiconductor device, obtaining a limit gate length according to said representative impurity concentration distribution, calculating, for a semiconductor device of which a gate length is equal to or greater than said limit gate length and equal to or less than said upper-limit gate length, an impurity concentration distribution of the semiconductor device according to said representative impurity concentration distribution, and obtaining characteristics of the semiconductor device according to the impurity concentration distribution thus calculated.
According to one aspect of the present invention, there is provided a program to be executed by a computer, comprising the processing steps of inputting an upper-limit gate length of a semiconductor device including a gate electrode on or above a partial area of a surface of a semiconductor substrate, inputting an impurity implantation condition, calculating, for a semiconductor device of which a gate length is substantially equal to said upper-limit gate length, a representative impurity concentration distribution under the impurity implantation condition, obtaining a limit gate length according to said representative impurity concentration distribution, obtaining, for a semiconductor device of which a gate length is equal to or greater than said limit gate length and equal to or less than said upper-limit length, an impurity concentration distribution of said semiconductor device according to said representative impurity concentration distribution, and calculating characteristics of said semiconductor device according to the impurity concentration distribution.
Once the limit gate length is obtained, characteristics can be obtained, for a semiconductor device of which a gate length is greater than the limit gate length and is equal to or less than the upper-limit gate length, without calculating the impurity concentration distribution under the impurity implantation condition or the like.
As a result, in a simulation processing to obtain characteristics of many semiconductor devices, the number of process simulations can be reduced. This minimizes the simulation time.
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Fujitsu Limited
Lee Jr. Granvill D
Smith Matthew
Staas & Halsey , LLP
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