Method of building a variety of complex high performance IC devi

Metal working – Method of mechanical manufacture – Electrical device making

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29825, H05K 336

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049551310

ABSTRACT:
A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density high-performance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carriers in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring one or more modules as test modules and either plugging them into modules to be tested or making them a permanent part of the device's module array.

REFERENCES:
The Impact of Silicon interconnect Technology on the Design Engineer by C. C. Perkins Sr. et al. IEEE Conf. 1987, Electro /87 & Minr/Micro Northeast, pp. 36/2/ 1-4.
Diserete Wafer Scale Integration by R. R. Johnson, Water Scale Integration, Proc of the IFIP WG 10.5 Workshop, pp. 345-352, 1986 ed by G. Sancier et al.
Silicon-on-Silicon Hybrids are Coming Into Their Own by Jerry Lyman, Electronics May 1987, N60, p. 11 N47(2).
Mosaic, A Modulas Architecture for VLSI System Circuits by J. Alves Conference: VLSI81, Very Large Scale Integration, Proceedings 8/18-21/81, pp. 53-61.

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