Patent
1993-09-10
1996-02-13
Nguyen, Hoa T.
39518221, 06F 1100, G06F 1100
Patent
active
054917883
ABSTRACT:
A multiprocessor computer system handles the failure of one or more of its processors without totally disabling the system. On power up, all of the CPUs are deactivated except for a CPU in a first physical slot. The power on self test routines review a log of errors and determine if certain critical errors have previously occurred. If so, the CPU in the first physical slot halts operation entirely. If the CPU in the first physical slot is not functioning properly or is halted, the hardware then awakens a CPU in a second physical slot, designates it as the first logical CPU, and the CPU then performs similar diagnostic checks. If it fails, the hardware again tries a third physical CPU and so on. When one CPU passes the initial error review, it proceeds with initialization of the computer system and performs further self testing. If it functions properly, it is designated as the first logical CPU, and retains its designation until the power is cycled. This first logical CPU then awakens the remaining CPUs and boots the rest of the system. If it fails this later self testing by having certain critical errors occur, the logical CPU 0 designation is transferred to another active CPU and the old CPU is halted. The new CPU commences operation effectively where the old CPU halted, so that system initialization is continued not restarted. The power on self test routines then further test the CPU in the first physical slot. Thus, if at least one CPU is operational, the computer system boots and operates.
REFERENCES:
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patent: 5155731 (1992-10-01), Yamaguchi
patent: 5247659 (1993-09-01), Curran et al.
patent: 5408647 (1995-04-01), Landry
patent: 5418955 (1995-05-01), Ikeda et al.
Cepulis Darren J.
Gagliardi Louis R.
Compaq Computer Corp.
Nguyen Hoa T.
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