Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-07-30
2004-11-23
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S720000, C438S766000, C438S769000
Reexamination Certificate
active
06821904
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of layers of different thickness gate oxide for application in the creation of dual gate electrodes.
(2) Description of the Prior Art
Improved semiconductor performance of semiconductor devices has been made possible by improvements in a range of related technologies, in device designs and in device packaging approaches.
The creation of many of the semiconductor devices starts with the growing of a layer of gate oxide over the surface where the device is to be located. The gate oxide is a thin thermal oxide, which allows better adhesion between the overlying layers (for instance nitride) and the (underlying) silicon and acts as a stress relaxation layer during field oxidation. Gate oxide can be formed by thermal oxidation of the underlying silicon and can also be formed in conjunction with a deposited oxide layer, nitride layer or any other material suitable for use as a gate dielectric. Gate oxide is usually formed as a silicon dioxide material but may be a composite oxide, such as TEOS and silicon dioxide, or a nitride oxide layer or a like gate dielectric. A gate oxide layer can for instance be grown in an oxidation steam ambient at a temperature between about 850 and 1,000 degrees C. to a thickness between about 10 and 250 Angstrom.
Device performance is highly dependent on the thickness of the layer of gate oxide. In devices that combine Field Effect Transistor (FET) devices with surrounding logic devices, the combined function that is provided by one semiconductor device requires the deposition of gate oxide layers of different thickness. Typically, surrounding logic functions require the use of a thin layer of gate oxide to enhance overall device performance while a thicker gate oxide is required in view of the required higher gate voltage for the FET access transistor of DRAM cells. As an example, with a voltage bias of about 2 volts of the substrate on which a FET memory device is created, a voltage difference of about 5 volts is required between the gate electrode and the substrate resulting in a gate voltage of 7 volts for the FET access transistor of the memory cells. The FET devices of the logic portion of the circuit however require a gate voltage of about 3.3 volts, making it clear that layers of pad oxide are required for these devices that are of different thickness.
Another application where gate oxide layers of different thickness is required is in the application of MOS devices where combined PMOS and NMOS devices are created that form a converter. The majority carriers of PMOS devices are holes; the majority carriers of NMOS devices are electrons. Holes have a considerable lower mobility than electrons resulting in a lower drive capability of the PMOS device. To compensate for this and to equalize the drive capability of the two types of devices, either the gate of the PMOS device is widened (allowing more drive current for a given gate voltage) or the thickness of the gate oxide layers for the two types of devices is adjusted allowing for higher gate current while maintaining gate widths the same. Of these two solutions, the varying of the thickness of the gate oxide is the more promising since the widening of the gate electrode requires surface area, which is contrary to the desire of miniaturization of the devices.
The invention addresses a method of creating layers of gate oxide of different thickness whereby a first, relatively thick layer is created and which is then partially and selectively reduced in thickness in order to create the relatively thin layer of gate oxide. The invention specifically addresses the desire for the presence of N
2
in the oxide of the layer of gate oxide since this presence provides improved signal to noise performance of the created gate electrodes.
U.S. Pat. No. 6,110,842 (Okuno et al.) shows a dual gate process using nitridation.
U.S. Pat. No. 5,254,489 (Nakata) shows a dual gate dielectric process by forming first and second oxide films using nitridation.
U.S. Pat. No. 6,303,521 B1 (Jenq) reveals a multi-thickness gate dielectric process.
U.S. Pat. No. 6,261,972 B1 (Tews et al.) discloses another dual gate oxide process.
SUMMARY OF THE INVENTION
A principle objective of the invention is to create a layer of gate oxide that does not have a negative effect of the signal-to-noise performance of the therewith-created gate electrode.
Another objective of the invention is to create layers of gate oxide having a different thickness whereby the relatively thin layer of gate oxide is provided with a higher concentration of nitrogen, thereby improving the signal-to-noise performance of the gate electrode created with the thin layer of gate oxide.
In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N
2
atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.
REFERENCES:
patent: 5254489 (1993-10-01), Nakata
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6261972 (2001-07-01), Tews et al.
patent: 6303521 (2001-10-01), Jenq
patent: 6331492 (2001-12-01), Misium et al.
patent: 6589877 (2003-07-01), Thakur
Chu Sanford
Ng Chit Hwei
Pradeep Yelehanka Ramachandramurthy
Verma Purakh
Zheng Jia Zhen
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saik George D.
Vinh Lan
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