Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-10-25
2001-05-29
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185120, C365S185180
Reexamination Certificate
active
06240020
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of bitline shielding in conjunction with a precharging scheme for flash memory devices. More particularly, this bitline shielding method allows for improved sensing of the core cell bit in NAND-based flash memory devices.
The overall array architecture for memory section of a typical NAND-based flash memory device comprises a core memory accessed by an upper and lower bank of page buffers and a right and left bank of word line decoders. The core memory contains information stored in blocks of memory and individual memory cells within the blocks. The right and left word line decoders are used to access specific memory cells within each memory block and the upper and lower bank of page buffers provide the input and output circuitry for each memory cell.
The architecture of one core cell block in the typical NAND-based flash memory device comprises the individual memory elements and select gates. The memory elements and select gates are embodied in non-volatile, floating gate transistors that may be programmed to a logic state of 0, 1 or other states, depending on the particular type of transistor and programming used. The control gates of the transistors that comprise the individual memory elements and select gates in each core cell block are addressed by word lines controlled by the addressing system. The memory elements are connected in series with each other and the select gates. The select gates, at the ends of the chain of memory cells, are connected with either the array common voltage Vss or a bitline. A page buffer is connected with a core cell block via a bitline. The page buffer includes transistors and supporting circuitry that regulate the flow of data into and out of the core cell block and into and out of the external system.
A problem is that the bitline inherently has a large capacitance associated with it due to the proximity of other bitlines. Thus, the bitline has a relatively slow speed of response when data is extracted, or read, from memory elements due to the necessary charging and discharging time. Typically, the time it takes to charge the bitline to the voltage level necessary for sensing is larger than the time it takes to discharge the bitline. Thus, to decrease the cycle time for reading a specific word line, it is more advantageous to decrease the charging time rather than the discharging time.
Previous precharging schemes propose either a mechanism or a method for solving this problem. However, in addition to the charging problems stated above, the capacitance causes another problem to occur after precharging, during evaluation or sensing of a particular memory cell. As described above, a large capacitance exists between neighboring bitlines because of their relative proximity to each other. The problem lies in that if a bitline is pulled close to ground during sensing, neighboring bitlines that are supposed to be held constant at the sensing voltage, are instead coupled via the capacitance to this bitline. In this case, the advantage of precharging the bitline is significantly reduced as the bitline that is supposed to be held at the sensing voltage must be recharged to the sensing voltage from some intermediate voltage point between the sensing voltage and ground before evaluation can be executed.
FIG. 8
shows a combination of the page buffers and bitlines with capacitive coupling between bitlines in a typical NAND-based flash device. In this figure, neighboring bitlines are associated with alternate banks of page buffers. For example, the first bitline
500
is associated with the upper bank of page buffers
510
, the second bitline
501
is associated with the lower bank of page buffers
520
, the third bitline
502
is associated with the upper bank of page buffers
500
, etc. . . . The effect of the capacitative coupling between the bitlines due the their proximity is indicated by the capacitors
550
,
551
, et al.
FIG. 9
illustrates the voltage vs. time diagram of a pair of precharged neighboring bitlines, e.g.
500
and
501
, the first bitline
500
is pulled down from the sensing voltage to close to ground (Vss) during sensing and the second
501
is supposed to be held at the sensing voltage. The solid line depicts the bitline discharged to near Vss and the dashed line illustrates the neighboring bitline. As shown, at time T
pc
both bitlines start precharging. The voltages on both bitlines precharge to V
high
at time T
h
in a time T
prec
and are held at this voltage until the sensing time, T
eval
. At T
eval
, the voltage of the first bitline is discharged over time T
disc
until time T
L
, at which point the voltage reaches V
low
. The voltage of the other bitline decreases to V
int
during effectively the same period. It then takes time T
rech
to recharge the second bitline to V
high
. It takes a time T
read
from T
eval
until the voltage of the second bitline may be read accurately.
Similarly,
FIG. 9
also illustrates the voltage vs. time diagram of a pair of precharged next neighbor bitlines as depicted in FIG.
8
. The voltage vs. time diagram is valid assuming the intermediate bitline is left floating while the other bitlines are active (or being sensed). This is to say that the extra recharging period for a bitline is also necessary if the first bitline
500
is pulled to close to the ground voltage and the third bitline
502
is left floating at the sensing voltage. This occurs when the upper bank of bitlines
510
is active while the lower bank of bitlines
520
is inactive and the associated bitlines, like the intermediate bitline
501
, are floating.
In either case, the time necessary for accurate sensing of a specific memory element, and thus bitline, is increased.
BRIEF SUMMARY OF THE INVENTION
In view of the above, a method of bitline shielding in conjunction with a precharging scheme for a flash memory device is provided.
In a first aspect of the present invention, the bitline shielding arrangement comprises a flash memory device. The flash memory device comprises a plurality of core cell blocks containing flash memory cells, a plurality of page buffers and a plurality of bitlines. Each of the page buffers is in communication with all of the core cell blocks via a unique bitline. The bitlines are contained in two sets that are arranged such that at least one of the second set of bitlines is disposed between each of the first set of bitlines.
The method according to the first aspect of the invention comprises charging the first set of bitlines to a preset voltage during a first portion of a precharge cycle and the second set of bitlines to a second preset voltage. The second set of bitlines are charged concurrent with the first set of bitlines being charged and attain the second preset voltage either before or at the same time as the first set of bitlines attain the first preset voltage. Additionally, the logic state of at least one of the flash memory cells may be evaluated after the first set bitlines have attained the first preset voltage. Each of the flash memory cells undergoing evaluation is connected with a unique bitline contained in the first set of bitlines.
In addition, each page buffer in the flash memory device further comprises a latch and a transistor connected with both the latch and ground. The method according to the first aspect of the invention may further comprise grounding one side of the latch contained in at least each page buffer connected with one of the first set of bitlines via the transistor. The grounding occurs prior to the first set of bitlines attaining the first preset voltage.
A second aspect of the present invention is also directed towards a method of bitline shielding for a flash memory device. The flash memory device comprises a plurality of core cell blocks containing flash memory cells, a plurality of page buffers and a plurality of bitlines. Each of the page buffers is in communication with all of the core cell blocks via a unique bitline. The bitlines are contained two sets arranged such that at least
Chen Pau-Ling
Hollmer Shane
Yang Andrew
Advanced Micro Devices
Auduong Gene N.
Brinks Hofer Gilson & Lione
Hoang Huan
LandOfFree
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