Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-09-27
2001-02-27
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190
Reexamination Certificate
active
06195290
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of avoiding disturbance during the step of programming and erasing an electrically programmable semiconductor non-volatile memory device.
More particularly, the invention relates to a method for application in a semiconductor integrated non-volatile memory device having a single power supply and comprising a matrix of memory cells divided into sectors, and being programmable electrically in a byte mode, but the considerations made hereinafter would equally apply to any other type of flash memory, including flash memories with dual power supplies.
As is well known, read-only memories of the flash type, although non-volatile, allow information contained therein to be modified electrically during the write or program step and the erase step.
Memories of this type are constructed as matrices of cells arranged into rows, or word lines, and columns, or bit lines. Each cell comprises a floating gate transistor having a drain region and a source region formed on a semiconductor substrate and isolated by a channel region. The floating gate is formed over the substrate and isolated from the latter by a thin layer of gate oxide.
A control gate is coupled capacitively to the floating gate through a dielectric layer, and metallic electrodes are provided for contacting the drain, source, and control gate, in order to have predetermined voltage values applied to the memory cell.
Cells in the same word line have the electric line in common which drives their respective control gates, while cells in the same bit line have the drain terminals in common.
BACKGROUND OF THE INVENTION
When suitable voltage values are applied to a cell terminal, the cell state can be altered by changing the amount of the charge present at the floating gate. The operation whereby charge is stored into the floating gate is called “programming”, and consists of biasing the control gate and drain terminal at a predetermined value higher than the electric potential of the source terminal.
For example, each individual cell can be programmed by a electron injection process that allows electrons to become trapped within the floating gate when the control gate is applied a relatively high voltage, Vg, in the 9 to 12V range. Concurrently, the source terminal is connected to ground and the drain terminal is biased at a voltage Vb in the 4 to 7V range.
The programming of a flash memory can be performed either by the sector (page mode) or the byte (byte mode). In the former case, all the cells in one row of the matrix are addressed simultaneously. In the latter case, a single byte of the many available in one row is addressed.
The use of positive voltages Vg and Vb with relatively high values poses more than one problem from the standpoint of possible disturbance to cells adjacent to those being programmed, such as those cells in the same bit line which are not to be programmed and have their control gates connected to ground.
This phenomenon may result in spurious erasing of the stressed cells. In all cases, programming noise is apt to make retention of the charge after prolonged read cycles less secure.
It is a primary object of the present invention to solve this problem.
Another problem occurs when erasing memory cells. To erase a flash memory cell, use is made of Fowler-Nordheim's tunneling effect. The source terminal is applied a voltage approximating the program voltage, and the drain terminal is kept floating, while the control gate is connected to ground or to a negative voltage reference.
Erasing can be performed by the individual sector or by multiple sectors, just as programming can. However, the erase time is a function of the number of write and erase cycles that have involved the various sectors of the flash memory, and grows with the age of the individual sector. This means essentially that various sectors of the memory device get old at different times, i.e. at different aging stages according to the number of write/erase cycles to which they have been subjected.
As an example, there may be some sectors in one device which have gone through 50 program/erase kilocycles, and others that have gone through less than ten such cycles. The concurrent erasing of several sectors having different ages may place serious problems on the youngest sectors, which would then be subjected to the erase voltages needed to have the oldest sectors erased for a longer time than is necessary.
The underlying technical problem of this invention is to provide a method of preventing, both during the programming and the erasing step, disturbance of an integrated memory device as previously indicated. This method has performance characteristics which extend the useful life of the memory device and overcome the drawbacks of state-of-art programming and erasing techniques.
SUMMARY OF THE INVENTION
The solutive idea on which this invention stands is one of carrying out a verify operation on a byte to be programmed, prior to it being applied the first program pulse. In particular, this idea provides a break in the rising transient of the drain voltage Vb for reading the byte to be programmed.
The features and advantages of a method according to the invention will be apparent from the following detailed description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
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“Developments in Programming Flash at 3V”Electronic Engineering, 65(798):62,65-66, Jun. 1993.
Bartoli Simone
Dallabora Marco
Defendi Marco
Villa Corrado
Galanthay Theodore E.
Seed IP Law Group
STMicroelectronics S.r.l.
Tarleton E. Russell
Zarabian A.
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