Method of automatic wiring in a semiconductor device

Details Method of automatic wiring in a semiconductor device Method of automatic wiring in a semiconductor device

1991-09-26

1993-11-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437195, 437978, 437194, 257210, 257211, 257758, 257760, H01L 2144, H01L 2148

Patent

active

052643905

ABSTRACT:
A method of automatic wiring in a semiconductor integrated circuit device having four or more wiring layers, with the lowest layer being a terminal layer, is intended to overcome the prior art problem in which lower layers are mostly used for wiring and upper layers are not used efficiently. The method is designed to assign longer lines to upper layers distant from the terminal layer, and upper layers can have increased wiring densities with minimal numbers of lines, bends and through holes, thereby using upper layers efficiently.

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patent: 4746965 (1988-05-01), Nishi
patent: 4974049 (1990-11-01), Sueda et al.
patent: 5060045 (1991-10-01), Owada et al.
patent: 5140402 (1992-08-01), Murakata
K. A. Chen, et al., "The Chip Layout Problem: An Automatic Wiring Procedure", DA Conference (1977) pp. 298-302.

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