Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-07-14
2004-11-23
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S124000, C438S126000
Reexamination Certificate
active
06821818
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of assembling a semiconductor device, and more specifically to a method of assembling a semiconductor device forming an encapsulant.
2. Description of the Related Art
Referring to
FIG. 1A
, a plurality of semiconductor devices fabricated using conventional flip chip technology are shown. Substrate
100
a
has a plurality of packaging units
112
a
for assembling a plurality of the semiconductor devices. In
FIG. 1A
, as the name implies, flip chip technology is characterized by flipping over a semiconductor chip
10
a
for attachment to a substrate, through conductive bumps
12
a
. However, as is known, significant strain is imposed on the conductive bumps
12
a
during temperature cycling, when an organic material is used as the substrate. This strain results from the significant difference between the coefficient of thermal expansion between the organic substrate (14-17 ppm/° C.) and the silicon wafer (4 ppm/° C.). Consequently, the conductive bumps
12
a
deteriorate over time at an accelerated rate.
Therefore, to reduce this connection strain and enhance reliability, encapsulant
120
a
is usually filled into the space between the substrate
100
a
and the semiconductor chip
10
a
. In this way, stress is dispersed to the encapsulant to alleviate stress on the conductive bumps
12
a
. Thus, connection cracking is significantly reduced, and the life of the conductive bumps
12
a
is prolonged. In addition, the encapsulant
120
a
also prevents the transmission of leakage current caused by impurities between the conductive bumps
12
a
. Statistical data shows that the reliability of the device can be increased five to ten times when underfill encapsulation is utilized. Therefore, underfill encapsulation has become a highly important process. However, there are problems that arise in connection with the various ways of performing the underfilling process.
Conventionally, most flip chip packages are encapsulated by dispensing a liquid encapsulant with low viscosity along the periphery of the chip. Capillary action, generated from the encapsulant in the narrow space between the chip and the substrate, drives the encapsulant to fill the gap between the solder connections. Since filling is conducted by capillary action, it is very slow. For example, in a typical encapsulation operation, the filling takes several minutes to several tens of minutes depending on the filling temperature and chip size. Further, one encapsulating apparatus can only encapsulate a single chip in one run dispensing a liquid encapsulant with low viscosity along the periphery of the chip. The throughput per encapsulating apparatus is very low. Many encapsulating apparatuses are therefore necessary for mass production, negatively affecting the production cost. Furthermore, since capillary action alone is insufficient to fill all the space between the chip and the substrate, voids are easily formed in the encapsulant. Such voids require the flip chip package to be discarded from either popcorn effect, caused during subsequent thermal processes, or stress concentration, caused when the flip chip package is stressed.
Referring to
FIG. 1B
, a plurality of semiconductor devices fabricated using conventional wire-bonding technology are shown. Substrate
100
b
has a plurality of packaging units
112
b
for assembling a plurality of the semiconductor devices. Semiconductor chips
10
b
are respectively attached to packaging units
112
b
and connect to substrate
100
b
using wires
12
b
. Semiconductor chips
10
b
and wires
12
b
are covered by a molding compound
120
b
. Further, another package type, tape automatic bonding (TAB), may be produced when a substrate with a plurality of pre-formed leads (not shown) is used rather than the substrate
100
b
and wires
12
b.
When the semiconductor devices fabricated using conventional wire-bonding or TAB technology are encapsulated using a liquid encapsulant, a plurality of semiconductor devices can be encapsulated at the same time, but voids are still easily formed in the encapsulant.
Referring to
FIG. 1C
, a plurality of semiconductor devices of multi-chip module (MCM) type fabricated using stacked-die technology are shown. Substrate
100
c
has a plurality of packaging units
112
c
for assembling a plurality of the semiconductor devices. Semiconductor chips
10
c
are respectively attached to every packaging unit
112
c
and electrically connect to substrate
100
c
through conductive bumps
12
c
. Semiconductor chips
10
d
are respectively attached to and stacked overlying each semiconductor device
10
c
and electrically connect to substrate
100
c
through wires
12
d
. Spaces between the substrate
100
c
and semiconductor chips
10
c
are filled by underfill
120
c
. Semiconductor chips
10
d
, wires
12
d
, and underfill
120
c
are covered using a molding compound
120
d
. Further, a substrate with both flip chip and TAB type (not shown) may be provided rather than the substrate
100
c
, using a plurality of leads (not shown) electrically connecting the substrate and semiconductor chips
10
d.
The semiconductor device of MCM type shown in
FIG. 1C
faces challenges in process complexity, process yield, and product reliability resulting from using a plurality of assembling technologies such as flip chip, wire-bonding, and TAB. The aforementioned problems in flip chip package, wire-bonding package, and TAB package will occur at the same time when fabricating the semiconductor device of MCM type. Compared to the semiconductor device fabricated using other assembling technologies, there is further an interface between the underfill
120
c
and molding compound
120
d
, a negative factor affecting the process yield and product reliability of the semiconductor device of MCM type.
Solutions for the void in the encapsulant of the semiconductor device have been disclosed. U.S. Pat. Nos. 5,834,339 and 6,107,123 respectively disclose a method characterized as sealing a gap between a chip and a substrate with a fluid, curable encapsulant using the application of a uniform pressure such as an isostatic or hydrostatic pressure thereto for removal of voids and gas bubbles in the encapsulant. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, an extra tooling is necessary to control the encapsulant flow when applying the uniform pressure, negatively affecting the production cost. Furthermore, the method can only be used in the underfill process. U.S. Pat. No. 6,000,924 discloses a method and device providing a special mold to surround a chip to be encapsulated in a cavity, with an encapsulant injected into the cavity at an elevated pressure, and possibly at an elevated temperature. However, the mold must be specially designed to match the size of the chip to be encapsulated, negatively affecting production cost. Further, the mold still can only encapsulate a single chip in one run, thus the throughput of the mold is not improved. U.S. Pat. No. 6,187,613 discloses a process placing a metal foil on a flip chip that has been connected to a substrate, then applying downward pressure to the metal foil so as to form space between the metal foil, flip chip, and substrate, and filling an encapsulant into the space under pressure. The metal foil is about 0.01 mm to 0.1 mm thick and can withstand an encapsulating pressure exceeding 100 psi. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, the metal foil is very expensive and may be deformed under pressure, negatively affecting the uniformity of the sizes of the encapsulated flip chips. Furthermore, the process still can only encapsulate a single chip in one run, thus the throughput is not improved.
U.S. Pat. No. 6,046,076 discloses a method of encapsulating a microelectronic assembly applying a flowable encapsulant to the assembly while maintaining the assembly at sub-atmospheric pressure, then bringing
Chen Kai-Chi
Li Hsun-Tien
Brewster William M.
Industrial Technology Research Institute
Quintero Law Office
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