Method of assembling a multi-chip device

Details Method of assembling a multi-chip device Method of assembling a multi-chip device

1999-09-17

2004-08-31

Chang, Richard (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S830000, C029S832000, C029S593000, C174S255000, C257S723000, C257S724000, C361S767000, C361S768000, C324S755090, C324S765010

Reexamination Certificate

active

06782611

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to chip carriers, and more specifically, to a multi-chip land grid array carrier.
2. Description of Related Art
Computer processors include various cache memories, including memory caches and disk caches. A memory cache is a portion of memory made of high-speed static random access memory (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory. Memory caching is effective because most programs access the same data or instructions over and over. By keeping as much of this information as possible in SRAM, the computer avoids accessing the slower DRAM.
Some memory caches are built into the architecture of microprocessors. Such internal caches are often called primary, or Level
1
(L
1
) caches. Many computers also come with external cache memory, called Level
2
(L
2
) caches. The L
2
cache is coupled to a dedicated bus, sometimes referred to as a “backside bus.” Like L
1
caches, L
2
caches are composed of SRAM but they are typically much larger. The L
2
cache improves system-level performance by improving the processor's memory read and write performance, as well as decreasing the system bus utilization. The large L
2
cache results in less processor read requirements to main memory, thereby reducing the number of times the processor needs to access the system bus.
For example, the Intel® Pentium® Pro processor package includes the microprocessor chip and an L
2
cache die packaged in a single package. The microprocessor chip and the L
2
cache memory die are both mounted in a dual-cavity microprocessor package. The microprocessor package may then be mounted on a system motherboard. The tight coupling of the microprocessor chip and the L
2
cache improves system performance and efficiency. The Pentium® Pro processor architecture is described in the Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, 1996/1997, available from Intel® Corporation, and in
Pentium® Pro Processor System Architecture
, Mindshare, Inc., 1997, both of which are incorporated by reference herein in their entirety.
While cache devices are often implemented using multiple memory chips, a design such as the Pentium® Pro L
2
cache comprises a single die. The size of the L
2
cache varies according to various models of the Pentium® Pro available. For example, the processor may be implemented with 256 KB, 512 KB, 1 MB, etc. of L
2
cache capacity. Manufacturing the single, large memory die for the L
2
cache may be difficult and expensive. Defects in a single-die L
2
cache may not be discoverable until after the processor and L
2
cache die are assembled into their shared package. If a defect is found in the L
2
cache after it is assembled into the microprocessor package, the entire package often must be scrapped. Thus, it may be desirable to implement the L
2
cache in a manner that allows additional flexibility and simplifies manufacturing and testing.
Mounting the cache memory chips directly to a motherboard, as in many prior art cache implementations, greatly reduces performance. With cache memory implemented on the motherboard, each semiconductor die comprising the memory device is typically mounted in a conventional single-die package. The single-die packages are then soldered directly to the motherboard or mounted in sockets. The speed at which the cache runs is significantly slower when implemented on the motherboard.
In a compromise solution, single-die memory devices are coupled to a daughterboard along with the microprocessor. The daughterboard is then plugged into the motherboard. While this cache implementation improves performance over directly mounting the cache memory packages on the motherboard, it requires a larger footprint since the cache comprises several conventional single-die packages. Moreover, the daughterboard implementation still operates at a significantly slower speed than an integrated L
2
cache. In one prior art daughterboard L
2
cache implementation, the L
2
cache operates at only half the speed of the processor.
Rather than using several single-die memory devices for an L
2
cache, several semiconductor dice could be directly mounted in a processor package using conventional methods, such as controlled collapse chip connection (C
4
). This also has drawbacks. For example, the memory device semiconductor die may not be tested until mounted along with the microprocessor chip. If a single memory chip is defective, the entire microprocessor package must be scrapped, as removing and replacing a single semiconductor die is, at best, very difficult if not impossible.
The present invention addresses some of the above mentioned and other problems of the prior art.
SUMMARY OF THE INVENTION
In one aspect of the invention, a land grid array (LGA) carrier includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conductive pads coupled thereto.
In another aspect of the invention a method of assembling a multi-chip device includes fabricating an interposer having a first surface and a second surface and populating the second surface with a plurality of conductive pads. A solder ball is coupled to each of predefined conductive pads, and a plurality of semiconductor dice and a plurality of passive devices are coupled to the first surface.


REFERENCES:
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patent: 5483421 (1996-01-01), Gedney et al.
patent: 5635847 (1997-06-01), Seidel
patent: 5680936 (1997-10-01), Beers
patent: 5689091 (1997-11-01), Hamzehdoost et al.
patent: 5983490 (1999-11-01), Sakemi
patent: 5990564 (1999-11-01), Degani et al.

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