Method of arranging components in semiconductor device

Details Method of arranging components in semiconductor device Method of arranging components in semiconductor device

1995-06-06

1996-05-21

Trans, Vincent N.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

055196314

ABSTRACT:
A method of arranging components in a semiconductor device on a substrate (11), comprising provisionally determining a wiring path (3) so that a predetermined wiring capacitance is not exceeded in a specific network (1) and then performing a wiring process of elements (12) in the specific network within a component placement region (2) determined by the wiring path.

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"LAS: Layout Pattern Analysis System With New Approach" by Y. Okamura et al., IEEE 1982, pp. 308-311.
"Circuit Placement for Predictable Performance" by Hauge et al., IEEE 1987, pp. 88-91.
Research Disclosure, Method to Achieve Equal Capacitance on a Group of Nets During Circuit Layout and Placement, Mar. 1989, New York, NY, US.
IBM Technical Disclosure Bulletin, Method for Controlling VLSI Chip Timing Constraints, Mar. 1988, vol. 30, No. 10, p. 172, Armonk, NY, US.
IBM Thomas J. Watson, Research Center, Circuit Placement for Predictable Performance, 1987, pp. 88-91, Yorktown Heights, New York.
Yasushi Ogawa et al., Efficient Placement Algortthms Optimizing Delay for High-Speed ECL Masterslice LST's.

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