Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-11-16
2004-01-13
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S115000, C438S124000, C438S126000, C438S127000, C228S180210, C228S180220
Reexamination Certificate
active
06677179
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
Semiconductor devices (e.g., flip chips) have rapidly been advanced. One important trend of developing semiconductor device is the miniaturization of the products by employing high-density components, HDI, etc. However, the reliability of semiconductor devices is a challenging topic. Due to the large coefficient of thermal expansion mismatch between silicon chips, laminate board (i.e., substrate) and solder interconnects, failure of the semiconductor devices is a major concern. In order to improve the reliability of the semiconductor devices, underfill encapsulants have been developed to reinforce physical, mechanical and electrical properties of the solder joints connecting the chip and substrate, which can dramatically enhance fatigue life. They can also be used in a variety of organic and inorganic substrate materials, resulting in ten to hundred fold improvement in fatigue life as compared to an unencapsulated package. The new technique of underfill encapsulation has been increasingly accepted.
However, currently more than 90% of underfill encapsulants utilize capillary flow underfill, which relies on the use of capillary action to draw the underfill into the gap between the chip and substrate of the assembled package to complete the encapsulation process. There are two main disadvantages to this process: (1) The process of reflowing solder bump and the process of underfilling and curing the encapsulants are separated, which result in lower production efficiency. (2) The limit of capillary force results in the limit of flow distance for underfill materials, which further limits the chip size. As such it becomes a production bottleneck.
Other techniques are also currently in use. “No-flow” underfill (see, for example, U.S. Pat. No. 5,128,746) involves applying to the substrate surface an adhesive which includes a fluxing agent, applying the chip, and soldering it to the substrate. (“No-flow” refers to the fact that the underfill is applied before the component is attached. I.e., it does not have to be flowed under the attached component.) (See
FIG. 4
, herein, for a schematic of the no-flow process.) The underfill promotes adhesion of the solder, while the thermosetting adhesive cures to mechanically interconnect the chip and the substrate. However, this method is very difficult for applying heavily filled underfills. In addition, there is a significant difference between the high coefficient of thermal expansion (CTE) of unfilled underfill vs. the parts, further contributing to the poor reliability of the system.
A two-layer no-flow underfill system, described in Zhang et al (“A Novel Approach for Incorporating Silica Fillers into No-Flow Underfill”, Proceedings of 51st Electronic Components and Technologies Conference, pp. 310-316, (2001)) involves applying a coating with no filler to the base layer, followed by applying a coating that contains filler, and then applying the component. (See
FIG. 5
, herein, for a schematic of the process.) However, this multiple deposition process is difficult to handle. It results in high production costs and may lead to large differences in CTE.
A molded underfill method, in which the gaps between the chip and substrate are filled using as much as 70-90% filler, and the whole chip is encapsulated, is discussed in U.S. Pat. Nos. 6,038,136 and 6,157,086. Another system wherein underfill is predeposited onto a wafer before the wafer is cut into chips is proposed in WO 99/56312. In this method, it will be difficult to eliminate the air bubbles between the underfill and the substrate during the flip chip mounting stage, which could lead to poor adhesion of the underfill.
All of the existing techniques have one or more of the following negatives:
1. The silica fill interferes with getting a good solder joint, and there is a high solder defect level.
2. Depending on the size of the chip, when capillary flow underfill (i.e., underfill which flows under the chip by relying on capillary action) is added after the soldering is completed, the flow is frequently limited by the capillary forces.
3. The techniques are not high volume, low cost processes.
BRIEF SUMMARY OF THE INVENTION
A new method has been developed to provide underfill to chips mounted on substrates. First, an underfill is dispensed on the substrate. Second, the bumps of the chip are dipped in a flux that does not contain filler. Third, the chip that has been dipped in a tacky thermosettable flux is placed on the substrate, and fourth, the chip is soldered to the substrate, and simultaneously the underfill is cured. This process eliminates the interference on solder joints caused by the presence of filler in filled no-flow underfill. In addition, the fluxing property of the flux allows the use of underfills with emphasis on curing and mechanical properties instead of fluxing performance. Accordingly, a mounted device with reliable solder joints and underfill encapsulation is obtained.
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A Novel Approach to Incorporate Silica Filler into No-Flow Underfill, Zhuqing Zhang, et al., School of Materials Scie3nce and Engineering and Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, pp. 1-7.
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Pb-Free Epoxy Flip Chip Flux PK-002, Indium Corporation of America, Form No. 97728 R0.
Lee Ning-Cheng
Yin Wusheng
Indium Corporation of America
Weingarten Schurgin, Gagnebin & Lebovici LLP
Zarneke David A.
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