Method of and system for routing in a packet-switched communicat

Multiplex communications – Wide area network – Packet switching

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370 94, H04Q 1104, H04J 600

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active

043205003

ABSTRACT:
A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.

REFERENCES:
patent: 4074232 (1978-02-01), Otomo et al.
patent: 4168400 (1979-09-01), de Couasnon et al.
"A Minimum Delay Routing Algorithm using Distributed Computation", by Gallager, IEEE Transactions on Communications, vol. COM-25, No. 1, Jan. 1977, pp. 73-84.
"The Modeling of Adaptive Routing in Data-Communication Networks", by Segall, IEEE Transactions on Communications, vol. COM-25, No. 1, Jan. 1977, pp. 85-95.
"Problemi e Prospettive Della Commutazione Di Pacchetto", by Artom, Electronica e Telecomunicazioni, N. 5-1976, pp. 195-201.

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