Method of and system for evaluating bit errors in testing a sign

Details Method of and system for evaluating bit errors in testing a sign Method of and system for evaluating bit errors in testing a sign

1981-12-14

1984-01-24

Atkinson, Charles E.

Excavating

371 22, 375 10, H04B 1700, H04L 100

Patent

active

044280769

ABSTRACT:
In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

REFERENCES:
patent: 4070647 (1978-01-01), Robson
patent: 4363123 (1982-12-01), Grover
patent: 4385383 (1983-05-01), Karchevski
patent: 4387461 (1983-06-01), Evans
patent: 4393499 (1983-07-01), Evans

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