Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-06-10
2003-07-22
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S589000, C345S690000, C348S687000
Reexamination Certificate
active
06597333
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of and a system for controlling the brightness of a plasma display panel (hereinafter referred to as PDP), particularly for controlling the brightness of a picture reproduced from video signals and displayed on the PDP.
FIG. 10
is an explanatory view indicating a conventional driving system for driving an AC discharge type PDP whose luminescent units are arranged in a matrix manner.
As shown in
FIG. 10
, the conventional driving system has a signal processing section
1
for processing inputted composite video signals and for producing DVD driving signals, a display section
2
for receiving the DVD driving signals fed from the signal processing section
1
and for displaying reproduced picture on the PDP.
In the signal processing section
1
, composite video signals inputted from the outside are processed in an A/D converter
3
, so that said video signals will become in synchronism with a timing pulse produced from a timing pulse generating circuit
7
, and are converted into 8-bit digital picture element data signals which are then fed to a frame memory
4
.
The frame memory
4
, in accordance with a taking-in signal and a reading-out signal both of which are all fed from a memory control circuit
8
, is adapted to successively take-in picture element data from the digital picture element data signal fed from the A/D converter
3
, and to read-out the taken-in picture element data which is then fed to an output signal processing circuit
5
.
The output signal processing circuit
5
is provided to process the digital picture element data signal so as to produce for each field a picture element data signal having a mode (8 bit) corresponding to a brightness gradation of the filed. Then, the picture element data signal is synchronized with a timing signal fed from a timing signal generating circuit
9
and is further fed to a picture element data pulse generating circuit
10
.
In the signal processing section
1
, composite video signals inputted from the outside are also fed to a synchronizing signal separation circuit
6
which is provided to extract a horizontal synchronizing signal and a vertical synchronizing signal from the composite video signals. The extracted horizontal synchronizing signal and vertical synchronizing signal are then supplied to a timing pulse generating circuit
7
.
The timing pulse generating circuit
7
is provided to produce various timing pulses in accordance with the above horizontal and vertical synchronizing signals. The various timing pulses are fed to the A/D converter
3
, a memory control circuit
8
and a reading-out timing signal generating circuit
9
.
Here, the A/D converter
3
is provided to, in synchronism with the timing pulse fed from the timing pulse generating circuit
7
, perform analog/digital conversion for the composite video signals fed from the outside to the signal processing section
1
.
The memory control circuit
8
is provided to produce a taking-in signal (in synchronism with a timing pulse fed from the timing pulse generating circuit
7
) and a reading-out signal (in synchronism with a reading-out timing signal fed from the reading-out timing signal generating circuit
9
) to the frame memory
4
. Accordingly, the frame memory
4
can take-in picture element data from digital picture element data signal fed from the A/D converter
3
, and can read-out the taken-in picture element data.
The reading-out timing signal generating circuit
9
receives a timing pulse fed from the timing pulse generating circuit
7
, and produces a reading-out timing signal in accordance with said timing pulse. The reading-out timing signal is fed to the memory control circuit
8
, the output signal processing circuit
5
, further to a row electrode driving pulse generating circuit
11
of the display section
2
.
In this way, the memory control circuit
8
can produce a reading-out signal to the frame memory
4
, and the output signal processing circuit
5
can produce picture element data to a picture element data pulse generating circuit
10
of the display section
2
.
Referring to
FIG. 11
, the display section
2
comprises a PDP
12
which includes a plurality of row electrodes Xi, Yi (i=1, 2 . . . n) arranged in parallel with one another on an inner surface of a front glass substrate
12
A serving as a picture display panel.
Further, a dielectric layer
12
B is provided to cover the row electrodes Xi, Yi (i=1, 2 . . . n). A magnesium oxide (MgO) layer
12
C is formed on the dielectric layer
12
B, an electric discharge space
12
E is formed between the magnesium oxide layer
12
C and a rear glass substrate
12
D.
A plurality of column electrodes Dj (j=1, 2 . . . m) are arranged in parallel with one another on an inner surface of the rear glass substrate
12
D, in a manner such that the column electrodes Dj (j=1, 2 . . . m) are perpendicular to the row electrodes Xi, Yi (i=1, 2 . . . n).
In practice, each pair of row electrodes Xi, Yi are used to form one displaying line within the PDP, each intersection formed by one pair of row electrodes Xi, Yi with one column electrode Dj forms a picture element cell.
The picture element data pulse generating circuit
11
of the display section
2
is connected with the plurality of column electrodes Dj (j=1, 2 . . . m) for producing picture element data pulses DPj(j=1, 2 . . . m) corresponding to the picture element data fed from the output signal processing circuit
5
of the signal processing section
1
, said picture element data pulses DPj (j=1, 2 . . . m) being applied to the column electrodes Dj (i=1, 2 . . . m).
The row electrode driving pulse generating circuit
11
is connected with the plurality of row electrodes Xi, Yi (i=1, 2 . . . n), so as to produce the following pulses to these row electrodes Xi, Yi (i=1, 2 . . . n) in accordance with the reading-out timing signals fed from the reading-out timing signal generating circuit
9
of the signal processing section
1
. In fact, the pulses produced by the row electrode driving pulse generating circuit
11
and fed to the plurality of row electrodes Xi, Yi (i=1, 2 . . . n), are reset pulses RPx, RPy for effecting an electric discharge between each pair of row electrodes Xi, Yi (i=1, 2 . . . n) to generate charged particles in the discharge space
12
E, priming pulses PP for reforming the charged particles, scanning pulses SP for writing-in picture element data, sustaining pulses LPx, LPy for maintaining discharge luminescence, erasing pulses EP for erasing wall electric charges.
FIG. 12
is a timing chart indicating various timings of the above pulses to be applied to the row electrodes Xi, Yi (i=1, 2 . . . n).
As shown in
FIG. 12
, a reset pulse RPx of a positive voltage is applied to each of the row electrodes Xi (i=1, 2 . . . n), while another reset pulse RPy of a negative voltage is applied to each of the row electrodes Yi (i=1, 2 . . . n). With the application of the reset pulses RPx and RPy, an electric discharge is induced in a space between each pair of row electrodes Xi, Yi (i=1, 2 . . . n), whereby generating charged particles within the electric discharge space
12
E corresponding to all the picture element cells.
By virtue of the charged particles, upon completion of the electric discharge, a predetermined amount of wall charges will form in the same manner in all the picture element cells within the dielectric layer
12
B.
Here, a time period until the formation of the wall charges is called an all-at-once reset period.
On the other hand, the picture element data pulse generating circuit
10
operates to successively apply picture element data pulses DPj (j=1, 2 . . . m) (each having a voltage corresponding to picture element data) to the column electrodes Dj (j=1, 2 . . . m).
As shown in
FIG. 12
, just before the picture element data pulse generating circuit
10
applies picture element data pulse DPj (j=1, 2 . .
Hosoi Kenichiro
Kikuchi Nozomu
Sato Naruhiro
Todoroki Ryuichi
Arent Fox Kintner Plotkin & Kahn
Chow Dennis-Doon
Pioneer Electronic Corporation
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