Boots – shoes – and leggings
Patent
1994-02-01
1997-02-11
Mai, Tan V.
Boots, shoes, and leggings
364754, G06F 738, G06F 752
Patent
active
056027664
DESCRIPTION:
BRIEF SUMMARY
SUMMARY OF THE INVENTION
The invention relates to a method of forming the sum of a chain of products of each time two numbers which are successively supplied, each intermediate result of the summing operation being temporarily stored, and also relates to a device for forming the sum of a chain of products of each time a first and a second value, comprising a storage device for storing a number of values with a predetermined first number of bits, a clock-controlled control device for controlling the writing of values in registers, a first register device for storing each time two values to be multiplied by one another, a multiplier device comprising two inputs which are connected to the first register device, and a downstream product register which comprises an output for double the first number of bits, an adder device which comprises two sum inputs for each time the first number of bits, one of said inputs being connectable to the output of the product register, and a downstream sum register which consists of at least two partial sum registers for each time the first number of bits comprising an output which can be coupled to the other input of the adder device.
Methods of this kind are frequently used in digital signal processing, for example for the filming of signal waveforms and devices of this kind are used in many multipurpose signal processors. In order to enable the processing of signal sequences with a high frequency, customary signal processors comprise two data buses so as to enable the formation of a new product during each clock period. Because, moreover, this product contains double the number of bits, i.e. has double the word width, the adder device is also designed for double the word width. However, this represents a comparatively high expenditure.
It is an object of the invention to provide a method of the kind set forth which enables the formation of the sum of a chain of products with little expenditure and at the expense of only a slightly reduced speed.
This object is achieved in accordance with the invention in that the product produced by each separate multiplication is added to the intermediate result in two steps in that during the first step only the least-significant positions of the product are added to the corresponding positions of the intermediate result, the first partial sum thus formed being temporarily stored, whereas during the second step the remaining, more-significant positions of the product are added to the corresponding remaining positions of the intermediate sum and the carry of the first partial sum, the second partial sum thus formed being temporarily stored, during each step there being supplied another one of the numbers to be directly subsequently multiplied.
It is a further object of the invention to provide a device of the kind set forth which enables the formation of the sum of a chain of products with less expenditure and at the expense of only a slightly reduced speed.
This object is achieved in accordance with the invention in that the storage device is connected to the first register device via only one data bus for the first number of bits, and that the control device is conceived to operate alternately in a first and a second clock period and to apply, during the first clock period the first number of least-significant bits at the output of the product register and the contents of the second partial sum register to the inputs of the adder device, and to write, at the end of this clock period, one of the first values into the register device and the new partial sum appearing at the output of the adder device into the second partial sum register, and to apply, during the second clock period, the first number of most-significant bits at the output of the product register and the contents of the first partial sum register as well as a temporarily stored carry, to the adder device and to write, at the end of this clock period, one of the second values into the register device and the second partial sum appearing at the output of the adder device, into
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Bucklen et al, "Single-chip Digital Multipliers Form Basic DSP Building Blocks", EDN Electrical Design News, vol. 26, No. 7, Apr. 1, 1981 Newton, Mass., USA, pp. 153-163.
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Bauer Harald
Hellwig Karl
Lorenz Dietmar
Schuck Johannes
Barschall Anne E.
Mai Tan V.
U.S. Philips Corporation
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