Method of and circuit for controlling a clock

Details Method of and circuit for controlling a clock Method of and circuit for controlling a clock

2002-02-13

2003-11-25

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

C327S291000

Reexamination Certificate

active

06653871

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of and a circuit controlling switching of a clock to be used in a semiconductor integrated circuit such as a microcontroller or the like.
BACKGROUND OF THE INVENTION
In recent years, a clock in which original oscillation is multiplying by PLL is used in a microcontroller or the like, and as a result the high speed operation is realized. In such a situation, a high clock speed is required, but on the other hand a low speed operation is also required in order to establish low dissipation power operation. Therefore, the clock speed is switched according to objects, but it is necessary to carry out switching between a low clock speed and a high clock speed smoothly.
FIG. 1
is a block diagram showing a main section of the microcontroller into which a conventional clock control circuit is mounted. This microcontroller
1
is constituted so that a C-unit
2
for controlling switching of a clock, an E-unit
11
as a CPU core and a T-unit
12
for controlling an external bus interface are connected to an internal bus
13
.
The C-unit
2
has a bisecting divider (½)
21
for bisecting an external oscillation input (X
0
), a PLL
22
for multiplying the external oscillation input (X
0
), and a selector
23
for selecting any one of an output clock of the bisecting divider
21
and an output clock of the PLL
22
. The selector
23
selects a clock according to a stored value of a clock source switching register
24
. Moreover, the C-unit
2
has a CLKB-use nb divider (1
b)
25
for dividing the output clock of the selector
23
and outputting a clock CLKB for the CPU core, a CLKT-use nt divider (1
t)
26
for outputting a clock CLKT for the external bus interface, and a CLKP-use np divider (1
p)
27
for outputting a clock CLKP for a peripheral circuit. Dividing ratios of the CLKB-use nb divider (1
b)
25
, the CLKT-use nt divider (1
t)
26
and the CLKP-use np divider (1
p)
27
are set according to stored values of a dividing set register
28
.
After reset of the microcontroller
1
having the above structure is released, the microcontroller
1
is operated with bisection of the external oscillation input (X
0
) by the bisecting divider
21
. While it is being-operated with the bisection, various initializing operations are performed. After a multiplying rate of the PLL
22
is set and oscillation of the PLL
22
is stabilized, a dividing ratio is set in the dividing set register
28
so that a target frequency is obtained. Thereafter, in order to switch a supply clock to the internal circuit from bisection of the external oscillation input (X
0
) to a PLL clock, “1” is written into the clock source switching register
24
so that the PLL
22
is enabled. As a result, the internal clock of the microcontroller
1
is changed from a low speed into a high speed, and thus the microcontroller
1
is operated at high speed.
However, in the microcontroller
1
into which the above conventional clock control circuit is mounted, as shown in
FIG. 2
, when the clock source is switched from a low speed clock (for example, 2 MHz) into a high speed clock (for example, 64 MHz), dissipation current Icc of the internal circuit increases abruptly from 10 mA to 300 mA, for example. For this reason, a great voltage drop occurs, and an internal voltage Vcc is occasionally less than a guaranteed range. As a result, there arises a problem of a malfunction.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of and circuit for controlling clock in which it is possible to reduce a voltage fluctuation when a low speed clock is changed into a high speed clock and prevents an internal voltage from being less than a guaranteed range so as to be capable of avoiding occurrence of a malfunction.
In the clock control circuit according to one aspect of the present invention switching-over to a higher speed clock from a lower speed clock is carried out. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.
According to the above-mentioned aspect of this invention, when the clock is switched from low speed clock into high speed clock, the clock switching candidate device transitions to the sleep mode so that an internal resistance becomes great, and a degree of a voltage drop with respect to a time axis is reduced. Therefore, a guaranteed voltage can be maintained until the internal voltage is returned. Moreover, the candidate device transitions to the sleep mode so that a state at the time of the transition to the sleep mode is maintained in the clock switching candidate device.
Moreover, when a plurality of candidate devices in which the sleep mode is to be released exist, respective sleep signals to the plural candidate devices are released not simultaneously but gradationally. As a result, since a change in the internal resistance at the time of releasing the sleep signals becomes small, a degree of a change in a dissipation current becomes small, and a drop of the internal voltage can be slackened. Therefore, the guaranteed voltage can be maintained until the internal voltage is returned.
In addition, when a plurality of internal clocks exist, the switching of the clock source is carried out in every internal clock. As a result, since the plural internal clocks are switched into high speed clock not simultaneously but successively, a change width of the dissipation current is reduced, and the drop of the internal voltage can be slackened.
Moreover, when a clock source is switched from low speed clock into high speed clock, a clock speed is heightened gradationally. Since the clock speed becomes faster gradually, a change width of a dissipation current is reduced, and a drop of an internal voltage can be slackened. Moreover, the present invention may be constituted so that every time when the clock speed is heightened at one stage, transition to a sleep mode is once carried out, and the clock speed is switched into a faster speed at one more stage after returning to a normal mode. As a result, due to the transition to the sleep mode, as mentioned above, the guaranteed voltage can be maintained until the internal voltage is returned, and a state at the time of the transition to the sleep mode can be maintained.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5625311 (1997-04-01), Nakatsu
patent: 6084441 (2000-07-01), Kawai
patent: 6515519 (2003-02-01), Miyazaki et al.
patent: 10-011415 (1998-01-01), None
patent: 10-031531 (1998-02-01), None
patent: 11-003131 (1999-01-01), None

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