Method of and circuit for configuring a plurality of memory...

Details Method of and circuit for configuring a plurality of memory... Method of and circuit for configuring a plurality of memory...

2006-09-27

2010-12-14

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Addressing

Using selective matrix

C365S230020, C711S202000

Reexamination Certificate

active

07852705

ABSTRACT:
A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the plurality of memory elements; selecting a width for memory locations of the plurality of memory elements, the width for the memory location being less than the width of a data word; configuring the plurality of memory elements to have the selected width; and concatenating the outputs for the plurality of memory elements to generate a concatenated output comprising a data word. A circuit for configuring a plurality of memory elements having selectable dimensions is also disclosed.

REFERENCES:
patent: 6104836 (2000-08-01), Buckley et al.
patent: 7193895 (2007-03-01), Jin et al.
patent: 7254691 (2007-08-01), Ebeling
patent: 7386650 (2008-06-01), Watanabe
patent: 2003/0002474 (2003-01-01), Alexander et al.

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