Static information storage and retrieval – Powering – Conservation of power
Patent
1980-04-03
1982-05-18
Fears, Terrell W.
Static information storage and retrieval
Powering
Conservation of power
365149, 365189, G11C 1140
Patent
active
043308538
ABSTRACT:
Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.
REFERENCES:
patent: 3540010 (1970-11-01), Heightley et al.
patent: 3541531 (1970-11-01), Iwersen et al.
patent: 3643231 (1972-02-01), Lohrey et al.
patent: 3668264 (1972-08-01), Dingwall
patent: 3736477 (1973-05-01), Berger et al.
patent: 3736574 (1973-05-01), Gersbach
patent: 3786422 (1974-01-01), Alexander et al.
patent: 3815106 (1974-06-01), Wiedmann
patent: 3816758 (1974-06-01), Berger
patent: 3866531 (1975-05-01), McNeill
patent: 3900838 (1975-08-01), Wiedmann
patent: 3993918 (1976-11-01), Sinclair
patent: 4021786 (1977-05-01), Peterson
patent: 4032902 (1977-06-01), Herndon
patent: 4070656 (1978-01-01), Heuber et al.
patent: 4090255 (1978-05-01), Berger et al.
patent: 4112511 (1978-09-01), Heald
patent: 4185321 (1980-01-01), Iwahashi
"MTL Storage Cell", S. K. Wiedmann, IBM Tech. Dis. Bul., vol. 21, No. 1, Jun. 1978, pp. 231, 232.
"Merged-Transistor Logic (MTL)-A Low Cost Bipolar Logic Concept", Berger et al., IEEE Jour. of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 340-346.
"Integrated Injection Logic: A New Approach to LSI", by Hart et al., IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 346-351.
IBM TDB "Restore Circuitry for Bit/Sense System", by S. K. Wiedmann, vol. 13, No. 6, Nov. 1970, pp. 1705-1706.
IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, "A Fast 7.5 ns Access 1K-Bit RAM for Cache-Memory Systems", by K. Kawarada et al., pp. 656-663.
IEEE Journal of Solid-State Circuits, vol. SC-2, No. 4, Dec. 1967, "Beam-Lead Sealed-Junction Semiconductor Memory with Minimal Cell Complexity", by J. E. Iwersen et al., pp. 196-201.
IEEE Journal of Solid-State Circuits, vol. SC-6, No. 5, Oct. 1971, "Bipolar Dynamic Memory Cell", by H. H. Henn, pp. 297-300.
Electronics, May 2, 1974, "Current Steering Simplifies and Shrinks 1k Bipolar RAM", by J. E. Gersbach, pp. 110-114.
Electronics, vol. 47, No. 5, Mar. 7, 1974, "Pinch Load Resistors Shrink Bipolar Memory Cells", by S. K. Wiedmann, pp. 130-133.
Heimeier Helmut H.
Klein Wielfried
Klink Erich
Wernicke Friedrich C.
DeBruin Wesley
Fears Terrell W.
International Business Machines - Corporation
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