Method of and apparatus for testing A-D converter with a source

Details Method of and apparatus for testing A-D converter with a source Method of and apparatus for testing A-D converter with a source

1996-10-17

1999-02-09

Williams, Howard L.

Coded data generation or conversion

Converter calibration or testing

341118, 341161, 341156, 341158, H03M 110

Patent

active

058700420

ABSTRACT:
When an upper reference voltage is erroneously reduced below a normal value in a subranging A-D converter, a resistance block of a ladder resistance having a voltage lower than a proper one is selected and a lower reference voltage is necessarily reduced below an analog input voltage, so that all outputs of lower bits go high. Namely, a region (B1) where a current flowing to a comparator becomes constant without depending on the value of an analog input voltage (Vin) appears. Presence of abnormality can be determined by detecting this. Thus, a functional test or a static linearity test of an A-D converter cell is made while remarkably reducing the number of external test terminals.

REFERENCES:
patent: 4894656 (1990-01-01), Hwang
patent: 5070332 (1991-12-01), Kaller et al.
patent: 5223836 (1993-06-01), Komatsu
patent: 5581255 (1996-12-01), Hsu

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