Method of and apparatus for startup of a digital computer system

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 25, 331 27, 331 74, 331DIG2, 364DIG1, 364270, 395550, H03L 7095

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052948943

ABSTRACT:
A method of starting up a system clock that has been generated by a phase-locked loop, and circuitry for accomplishing that method. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks.

REFERENCES:
patent: 4310804 (1982-01-01), Ryon
Electronics Engineers'Handbook, 3rd ed. New York, McGraw-Hill Book Company, 1989, pp. 3-39; 3-42; 8-66; 13-13 through 13-16; 14-20 through 14-25; 22-25 through 22-26.
McGraw-Hill Encyclopedia of Science & Technology, 5th ed. New York, McGraw-Hill Book Company, pp. 134-136.
"The RCA COS/MOS Phase-Locked-Loop A Versatile Building Block for Micro-Power Digital and Analog Applications" in: RCA COS/MOS Integrated Circuits, 1978, RCA Corporation, pp. 598-601.

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