Static information storage and retrieval – Powering
Patent
1988-08-05
1990-02-27
Hecker, Stuart N.
Static information storage and retrieval
Powering
36518909, 36518903, 365242, 365227, 3072962, 3072968, G11C 700, G11C 800, H03K 301
Patent
active
049051997
ABSTRACT:
A circuit (50) is provided in a dynamic RAM (1) for detecting establishment of a substrate bias voltage (V.sub.BB) when the power is first turned on. A NAND gate (5d) in a clock generator circuit (10) immediately applies a high level signal to an inner circuit (11) when the power is turned on. Successively, the NAND gate (5d) applies a RAS signal to the inner circuit (11) in response to the establishment of V.sub.BB. Therefore, the dynamic RAM (1) is brought to a standby state immediately after the power is turned on and thereafter is controlled by the RAS signal. Consequently, flow of excessive current and latch-up immediately after the power is turned on can be prevented.
REFERENCES:
patent: 4780854 (1988-10-01), Watanabe et al.
patent: 4817055 (1989-03-01), Arakawa et al.
IEEE J. of Sol. St. Circuits: "A Fast 256kx4 CMOS DRAM with a Distributed Sense and Unique Restore Circuit" by H. Miyamoto et al, V. SC-22, No. 5, Oct. 1987, pp. 861-867.
IEEE J. of Sol. ST. Circuits: "A Reliable 1-Mbit DRAM with a Multi-Bit Test Mode" by M. Kumanoya et al, V. SC-20, No. 5, Oct. 1985, pp. 909-913.
Weste, Neil H. E. et al, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley Publishing Co., Reading MA: pp. 227-229.
Hecker Stuart N.
Koval Melissa J.
Mitsubishi Denki & Kabushiki Kaisha
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