Cleaning and liquid contact with solids – Processes – Including application of electrical radiant or wave energy...
Reexamination Certificate
1998-10-02
2002-07-16
Alanko, Anita (Department: 1746)
Cleaning and liquid contact with solids
Processes
Including application of electrical radiant or wave energy...
C134S021000, C216S012000, C216S013000, C216S045000, C216S075000, C156S345420
Reexamination Certificate
active
06418941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of the plasma cleaning of a chip-mounted board, which method is carried out before a wire bonding operation in which pads of a chip are connected respectively to electrodes of the board by wires. The invention also relates to apparatus for performing this method.
2. Related Art
There is known a technique in which the plasma cleaning of a board is carried out before a wire bonding operation in which pads of a semiconductor integrated circuit chip (hereinafter referred to merely as “chip”), mounted on the board, are connected respectively to electrodes of the board by wires. In the plasma cleaning, the board is received within a vacuum chamber, and a high-frequency voltage is applied to a plasma-generating electrode provided in the vacuum chamber so as to produce ions of positive charge and electrons of negative charge, and these ions and electrons are caused to impinge on the pads on an upper surface of the chip and the electrodes on the board, thereby cleaning these pads and electrodes. When the pads and the electrodes are thus cleaned, the wire bonding ability thereof is enhanced, and the wires can be firmly bonded to the pads and the electrodes.
However, when the above plasma cleaning of the board is carried out, a transistor structure portion within the chip is liable to be destroyed. The cause of this destruction has not yet been known, and this is one of the reasons why the plasma cleaning has not been extensively used. The present invention has been made in the process of clearing up the cause of this chip destruction, and the cause of the chip destruction, cleared up by the inventors of the present invention, will be explained in the following.
FIG. 5
is a cross-sectional view of an essential portion of a conventional apparatus for the plasma cleaning of a board. In this Figure, reference numeral
1
denotes the board to be subjected to the plasma cleaning. A land
2
is formed at a central portion of an upper surface of the board
1
, and electrodes
3
are formed on the upper surface of the board
1
, and are disposed around the land
2
. A chip
4
is adhesively bonded to an upper surface of the land
2
by a bond (adhesive)
6
. Pads
5
are formed on an upper surface of the chip
4
. The pads
5
are connected respectively to the electrodes
3
by wires in a later wire bonding step. The pads
5
and the electrodes
3
are subjected to a plasma cleaning treatment so as to enhance the wire bonding ability.
The bond
6
is formed by mixing powder of metal, such as Ag, into an epoxy resin. After this board
1
is completed, it is incorporated into an electronic equipment, and when an electric current is caused to flow through the chip
4
, heat is generated because of an internal resistance of the chip
4
. Therefore, the bond
6
contains the powder of metal having good thermal conductivity, such as Ag, so that the heat, generated by the chip
4
, can be transferred to the land
2
through the bond
6
.
The board
1
is placed on a plate-like, plasma-generating electrode
7
. A cover member
8
is provided to cover the plasma-generating electrode
7
, and a vacuum chamber
9
is defined by the cover member
8
and the electrode
7
. An AC power source
10
is connected to the plasma-generating electrode
7
so as to apply a high-frequency voltage to this electrode. The cover
8
is connected to a grounding portion
11
. The vacuum chamber
9
is evacuated to a vacuum by vacuum evacuation means, and plasma-generating gas, such as argon (Ar) gas, is supplied into the vacuum chamber
9
.
Next, the plasma cleaning operation will be described. The board
1
is placed on the plasma-generating electrode
7
, and the vacuum chamber
9
is evacuated to a vacuum by the vacuum evacuation means, and then Ar gas is supplied into the vacuum chamber
9
. Then, the AC power source
10
is driven to apply a high-frequency voltage to the electrode
7
. As a result, the interior of the vacuum chamber
9
is in a plasma condition, and ions Ar
+
of positive charge and electrons e
−
of negative charge are produced within the vacuum chamber
9
. The ions Ar
+
and the electrons e
−
impinge on the electrodes
3
of the board
1
and the pads
5
of the chip
4
, thereby cleaning the electrodes
3
and the pads
5
.
The board
1
is placed on a central portion of the plasma-generating electrode
7
, and therefore a peripheral portion of this electrode
7
is not covered with the board
1
, and is exposed to the vacuum chamber
9
. On the other hand, the high voltage having a high frequency is applied to the electrode
7
, so that the electrode
7
varies between a positive potential and a negative potential at a high frequency. As a result, the motion of the electrons e
−
becomes quite vigorous at the peripheral portion of the electrode
7
. In
FIG. 5
, broken-line arrows a show the electrons e
−
vigorously moving at the peripheral portion of the electrode
7
which is not covered with the board
1
. And besides, those electrons e
−
, which are present at the central portion of the vacuum chamber
9
above the chip
4
, avoid the board
1
, and move toward the peripheral portion of the vacuum chamber
9
(as indicated by broken-line arrows b), and make a vigorous motion as indicated by the broken-line arrows a.
Because of the above phenomenon, the amount of the ions Ar
+
of positive charge relatively increases at the central portion A of the vacuum chamber
9
while the amount of the electrons e
−
of negative charge relatively increases at the peripheral portion B of the vacuum chamber
9
. Namely, the distribution of the positive ions and the electrons within the vacuum chamber
9
becomes uneven. Therefore, the pads
5
of the chip
4
, located at the central portion A of the vacuum chamber
9
, are liable to be electrically positively charged while the electrodes
3
of the board
1
are liable to be electrically negatively charged.
With respect to the destruction of the chip, it is important to note that the land
2
is negatively charged with the electrons e
−
. More specifically, as shown in
FIG. 5
, the land
2
is much larger in size than the chip
4
, and a peripheral portion C of the land
2
is extending outwardly of the chip
4
, and is exposed, and the electrons e
−
impinge on this extending portion of the land
2
in a larger amount than the positive ions do, so that the land
2
is electrically negatively charged. On the other hand, the pads
5
of the chip
4
are positively charged as described aboved, and therefore a large potential difference occurs between the pads
5
and the land
2
. However, since the chip
4
is adhesively bonded to the land
2
by the electrically-conductive paste
6
, a large potential difference occurs between the pads
5
and the chip
4
, and as a result, a charge build-up current flows through a transistor structure portion, formed within the chip
4
, so that the transistor structure portion is destroyed by this current.
Next, explanation will be made of the relation between the size of the area of the extending (exposed) portion of the land
2
, extending outwardly of the chip
4
, and the potential difference between the pads
5
and the transistor structure portion.
FIGS. 6A
to
6
D are plan views showing various examples of chip-land arrangements, respectively. More specifically, in
FIG. 6A
, a chip
4
and a land
2
are equal in area to each other, and the land
2
does not extend outwardly of the chip
4
at all (The extension area is 0 mm
2
). In
FIG. 6B
, the area of an extending, exposed portion of a land
2
, extending outwardly of a chip
4
, is relatively small (The extension area is 30 mm
2
). In
FIG. 6C
, a chip
4
has a relatively small size, and the area of an extending, exposed portion of a land
2
, extending outwardly of the chip
4
, is relatively large (The extension area is 100 mm
2
). The arrangement of
FIG. 6D
differs from the arrangement of
FIG. 6C
Arita Kiyoshi
Asano Tanemasa
Alanko Anita
Matsushita Electric - Industrial Co., Ltd.
Olsen Allan
Stevens Davis Miller & Mosher LLP
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