Method of and apparatus for normalization of a floating point bi

Details Method of and apparatus for normalization of a floating point bi Method of and apparatus for normalization of a floating point bi

1993-04-20

1996-04-30

Bowler, Alyssa H.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

055133622

ABSTRACT:
A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M. A selecting circuit is adapted to supply, as the exponent e of the result, 0 when CR is equal to 1, and an output (E-LSA) of a subtracting circuit when CR is equal to 0. This enables the denormalize processing of a floating point binary number to be executed at a high speed equivalent to that at which a normalize processing is executed.

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