Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2000-12-14
2002-11-19
Wong, Edna (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S137000, C205S149000, C205S157000, C205S652000, C205S654000, C205S662000, C205S663000, C205S686000
Reexamination Certificate
active
06482307
ABSTRACT:
BACKGROUND OF THE INVENTION
Multi-level integrated circuit (IC) manufacturing requires many steps of metal and insulator film depositions followed by photoresist patterning and etching or other means of material removal. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines or channels. Often, these features need to be filled with a specific material such as a metal or other conductor. Once filled with a conductor, the features provide the means to electrically interconnect various parts of the IC.
Electrodeposition is a technique used in IC manufacturing for the deposition of a highly conductive material, such as copper (Cu), into the features on the semiconductor wafer surface. In electrodeposition or electrochemical plating of semiconductor wafers, electrical contact needs to be made to a wafer seed layer as well as to an electrolyte solution.
FIG. 1
is a schematic illustration of a wafer or substrate
16
to be coated with Cu. Features
1
may be vias, trenches, bond pads, etc., and are opened in the dielectric or insulator layer
2
. To achieve Cu deposition, a barrier layer
3
is first deposited over the whole wafer surface. Then, a conductive Cu seed layer
4
is deposited over the barrier layer
3
. An electrical contact is made to the barrier layer
3
and/or the seed layer
4
, the wafer surface is exposed to a Cu plating electrolyte, and a cathodic voltage is applied to the wafer surface with respect to an anode which also makes physical contact with the electrolyte. In this way, Cu is plated out of the electrolyte, onto the wafer surface, and into the features
1
.
The terms “wafer” and “substrate” are used interchangeably above and throughout the remaining description. Referring to the example shown in
FIG. 1
, it is to be understood that the “wafer” or “substrate” referred to includes the wafer WF per se, the dielectric or insulator layer
2
, and the barrier layer
3
, with or without the seed layer
4
. These terms, of course, may also refer to a wafer WF per se, including one or more previously processed layers, a further dielectric or insulator layer, and a further barrier layer, with or without a further seed layer.
The electrical contact to the seed layer and/or the barrier layer is typically made along the periphery of the wafer, which is usually round. This approach works well for thick and highly conductive seed layers and small wafer diameters (e.g. 200 mm) However, the trend in the semiconductor industry is to go to larger wafers (e.g. 300 mm) and smaller feature sizes (smaller than 0.18 microns). Smaller feature sizes, as well as cost considerations, require the use of the thinnest possible seed layers. As the wafer size increases, the plating current value also increases. As the seed layer thickness decreases, the sheet resistance increases, and the voltage drop between the middle and the edge of a large wafer also increases. Therefore, voltage drop becomes a major problem, especially for large wafers with thin seed layers. This voltage drop results in non-uniform Cu deposition on the wafer surface, with deposition in regions near the contacts being typically thicker than in other regions.
One other consideration in Cu plating is the “edge exclusion”.
Electrical contact to a wafer seed layer has been made, on a frontal side of the wafer, near the edge of the wafer using contacts that have been mechanically attached to a wafer chuck or spindle. Cu plating heads, such as the one described in commonly assigned, copending U.S. Patent application Ser. No. 09/472,523, filed Dec. 27, 1999, pending, titled WORK PIECE CARRIER HEAD FOR PLATING AND POLISHING, typically use contacts around peripheries of the wafers. Making electrical contact and, at the same time, providing a seal against possible electrolyte leakage, however, is difficult. Moreover making electrical contact in this way is undesirable due to its edge exclusion effect and may require cumbersome frontal sealing to protect the electrode contacts.
FIG. 2
shows a cross sectional view of the contacting scheme utilized in the carrier head of application Ser. No. 09/472,523. Here, the wafer or substrate
16
is contacted by a ring-shaped contact
17
which is sealed by a ring seal
18
against exposure to the electrolyte
9
a
. The seal
18
also prevents the electrolyte
9
a
from reaching the back surface of the wafer or substrate
16
. Such a contacting scheme extends a distance “W” from the edge of the wafer. The distance “W” is referred to as “edge exclusion” and may typically be 3-7 mm. Minimizing “W” would allow better utilization of the wafer surface for IC fabrication.
Various approaches to providing improved electrical contacts to the surfaces of semiconductor wafers during electrodeposition of conductors or during electro-etching or electro-polishing form the subject matter of commonly assigned, copending U.S. Patent application Ser. No. 09/685,934, filed Oct. 11, 2000, pending, titled DEVICE PROVIDING ELECTRICAL CONTACT TO THE SURFACE OF A SEMICONDUCTOR WORKPIECE DURING METAL PLATING AND METHOD OF PROVIDING SUCH CONTACT. The entire disclosure of copending U.S. Patent application Ser. No. 09/685,934 is incorporated herein by reference as non-essential material. A portion of the disclosure of this copending application, moreover, is reproduced here as background information to facilitate an understanding of the present invention.
A general depiction of one version of a plating apparatus is shown in FIG.
3
. This apparatus can also be used for plating and polishing as disclosed in commonly assigned application Ser. No. 09/201,929, filed Dec. 1, 1998, now U.S. Pat. No. 6,176,992, titled METHOD AND APPARATUS FOR ELECTROCHEMICAL MECHANICAL DEPOSITION, and commonly assigned, copending application Ser. No. 09/472,523 mentioned earlier. The disclosure of each of these applications is incorporated by reference herein as non-essential material. The carrier head
10
holds the wafer
16
. The wafer has the barrier layer and the seed layer (not shown in
FIG. 3
) deposited on its surface, and therefore its surface is conductive. The head can be rotated around a first axis
10
b
. It can also be moved in the x, y, and z directions. A pad
8
is placed on an anode plate
9
across from the wafer surface. The pad surface may itself be abrasive, or the pad may contain an abrasive material. Pad designs and structures form the subject matter of commonly assigned, copending application Ser. No. 09/511,278, filed Feb. 23, 2000, now U.S. Pat. No. 6,414,388,titled PAD DESIGNS AND STRUCTURES FOR A VERSATILE MATERIALS PROCESSING APPARATUS, and commonly assigned, copending application Ser. No. 09/621,969, filed Jul. 21, 2000, now U.S. Pat. No. 6,413,403, titled PAD DESIGNS AND STRUCTURES WITH IMPROVED FLUID DISTRIBUTION. The disclosure of each of these applications is incorporated by reference herein as non-essential material.
Electrolyte
9
a
is supplied to the wafer surface through openings in the anode plate and the pad as shown by the arrows in FIG.
3
. Commonly assigned, copending application Ser. No. 09/568,584, filed May 11, 2000, pending, titled ANODE ASSEMBLY FOR PLATING AND PLANARIZING A CONDUCTIVE LAYER, discloses an anode plate, while commonly assigned, copending application Ser. No. 09/544,558, filed Apr. 6, 2000, now U.S. Pat. NO. 6,354,916, titled MODIFIED PLATING SOLUTION FOR PLATING AND PLANARIZATION, discloses an electrolyte. The disclosure of each of these applications is also incorporated by reference herein as non-essential material. The electrolyte then flows over the edges of the pad into the chamber
9
c
to be re-circulated after cleaning/filtering/refurbishing. An electrical contact
9
d
is provided to the anode plate. The anode plate turns around the axis
10
c
. In some applications, the plate may also be translated in the x, y, and/or z directions. Axes
10
b
and
10
c
are substantially parallel to each other. The diameter of the pad
8
is typically smaller than the diameter of the wafer surfa
Ashjaee Jalal
Basol Bulent M.
Nagorski Boguslaw A.
Talieh Homayoun
Uzoh Cyprian
Crowell & Moring LLP
NuTool Inc.
Wong Edna
LandOfFree
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