Method of and apparatus for implementing fast orthogonal...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07870176

ABSTRACT:
A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising:a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computation unit for the one stage so that only one computation unit is required for the stage; and a controller configured and arranged so as to provide coefficients to the computational unit, and control the sizes of memory and multiplexing architecture in the storage unit; wherein the multipliers' coefficients, the coefficients of the computational unit, the sizes of memories, and multiplexing architecture, for each stage are modified as a function of the value of N.The architecture can be implemented as an integrated chip, and used in communication devices.

REFERENCES:
patent: 3783258 (1974-01-01), Chwastyk
patent: 5293330 (1994-03-01), Sayegh
patent: 6061705 (2000-05-01), Hellberg
patent: 6098088 (2000-08-01), He et al.
patent: 6237012 (2001-05-01), Ohgose
patent: 6735167 (2004-05-01), Nawa et al.
patent: 2003/0055861 (2003-03-01), Lai et al.
patent: 2004/0243656 (2004-12-01), Sung et al.
Tell et al. ,“A converged Hardware Solution for FFT, DCT, and Walsh Transform” , IEEE, pp. 609-612, 2003.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of and apparatus for implementing fast orthogonal... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of and apparatus for implementing fast orthogonal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of and apparatus for implementing fast orthogonal... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2728739

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.