Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
1999-02-17
2003-07-15
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
C345S630000, C345S215000, C345S534000, C345S538000, C345S543000, C345S564000, C348S563000, C348S564000, C348S569000
Reexamination Certificate
active
06593937
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of displaying on-screen-display graphics data on a display device. More particularly, the present invention relates to the field of displaying on-screen-display graphics data provided from a source device on a display device.
BACKGROUND OF THE INVENTION
The IEEE 1394-1995 standard, “1394 Standard For A High Performance Serial Bus,” is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. In addition, the IEEE 1394-1995 bus has a universal clock called the cycle timer. This clock is synchronized on all nodes. Isochronous data transfers are real-time transfers which take place based on the universal clock such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. An example of an ideal application for the transfer of data isochronously would be from a video recorder to a television set. The video recorder records images and sounds and saves the data in discrete chunks or packets. The video recorder then transfers each packet, representing the image and sound recorded over a limited time period, during that time period, for display by the television set. The IEEE 1394-1995 standard bus architecture provides multiple independent channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional reliable data transfer operations which take place as soon as arbitration is won and transfer a maximum amount of data from a source to a destination.
The IEEE 1394-1995 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-1995 standard defines a digital interface for the application thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-1995 standard is very thin in size compared to other bulkier cables used to connect such devices in other connection schemes. Devices can be added and removed from an IEEE 1394-1995 bus while the bus is operational. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides in a standard address space, an identification ROM, a standardized set of control registers and in addition, its own address space.
The IEEE 1394-1995 standard defines a protocol as illustrated in FIG.
1
. This protocol includes a serial bus management block
10
coupled to a transaction layer
12
, a link layer
14
and a physical layer
16
. The physical layer
16
provides the electrical and mechanical connection between a device and the IEEE 1394-1995 cable. The physical layer
16
also provides arbitration to ensure that all devices coupled to the IEEE 1394-1995 bus have arbitrated access to the bus as well as actual data transmission and reception. The link layer
14
provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing an un-acknowledged real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer
12
supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block
10
contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block
10
also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
A block diagram of a conventional home audio/video network including a television and a video cassette recorder (VCR) is illustrated in FIG.
2
. The television
20
is coupled to the VCR
40
. Video data and associated data are sent between the VCR
40
and the television
20
in a known manner.
Relevant internal components of the television
20
and the VCR
40
are also illustrated in FIG.
2
. The television
20
includes an interface
32
which sends and receives audio and video signals to and from the VCR
40
. The interface
32
is coupled to an audio/video switch
26
for directing audio/video signals to and from the VCR
40
. A cable/antenna interface circuit
30
is coupled to receive input signals from a coaxial cable or an antenna and to pass those signals through a tuner
28
to the audio/video switch
26
. The audio/video switch
26
is coupled to a video random access memory (VRAM) circuit
24
for providing the video signals from the cable/antenna interface
30
or the VCR
40
to the display
22
.
The VCR
40
includes a video source
46
, such as a video tape which is being played by the VCR
40
or a television input. The VCR
40
also includes a graphics source
48
which generates on-screen-display graphics to be displayed by the television
20
when the VCR
40
is sending data to be displayed by the television
20
. Such on-screen-display graphics include words or symbols representing commands being executed by the VCR
40
, such as PLAY, STOP, REWIND, FAST-FORWARD, PAUSE and RECORD. The on-screen-display graphics generated by the graphics source
48
typically also include a menu or menus displayed on the television
20
for the user which allow the user to program the VCR
40
. On-screen-display graphics generated by the graphics source
48
are provided to a mixer circuit
44
. The mixer circuit
44
also receives video data from the video source
46
. The mixer circuit
44
then combines the on-screen-display graphics from the graphics source
48
and the video data from the video source
46
into a video output which is transmitted through the interface circuit
42
to the television
20
. The video output from the VCR
40
is then processed by the television
20
and shown on the display
22
. The mixer circuit
44
will, as appropriate, either overlay the on-screen-display graphics onto the video data to form the video output or cause the video output to include only on-screen-display graphics from the graphics source
48
or video data from the video source
46
.
In an audio/video network including a digital television and a digital VCR coupled together by an IEEE 1394-1995 serial bus network, the video data from the VCR is typically transmitted in a digital format such as MPEG. The VCR is not typically responsible for encoding the video data in an MPEG format, but will record and transmit data previously encoded in a MPEG format by another source. In order for the VCR to have the ability to combine on-screen-display graphics with the video data, as described above, the VCR would have to include an MPEG encoder and have the ability to encode the on-screen-display graphics into an MPEG format and then combine the streams of data into a video output stream of data. Due to the cost of MPEG encoders, such a requirement is cost prohibitive in competitive consumer VCRs.
A home audio/video interoperability (HAVi) architecture is defined by “The HAVi Architecture: Specification of the Home Audio/Video Interoperability (HAVi) Architecture,” draft version 0.8n13, Sep. 16, 1998. The HAVi architecture is t
Eyer Mark Kenneth
Ludtke Harold Aaron
Smyers Scott D.
Bella Matthew C.
Haverstock & Owens LLP
Sajous Wesner
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