Boots – shoes – and leggings
Patent
1993-09-02
1996-02-20
Trans, Vincent N.
Boots, shoes, and leggings
364490, G06F 1750
Patent
active
054935091
ABSTRACT:
In graphic data representing a symbolic layout for a semiconductor integrated circuit, a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles are set. First, the graphic data is cut along said first cutting lines to produce a plurality of first segment data items. These first segment data items are each compacted in the direction of the second cutting line. These compacted first segment data items are connected according to the first cutting lines. This connected first segment data is cut along the second cutting lines to produce a plurality of second segment data items. These second segment data items are each compacted in the direction of the first cutting line. These compacted second segment data items are connected to one another to produce a compacted mask layout.
REFERENCES:
patent: 5079717 (1992-01-01), Mina
patent: 5267177 (1993-11-01), Sato et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5353235 (1994-10-01), Do et al.
patent: 5369596 (1994-11-01), Tokumaru
patent: 5381343 (1995-01-01), Bamji et al.
"Compaction Based Custom LSI Layout Design Method"by Ishikawa et al., IEEE ICCAD-85, Nov. 18-21, 1985, pp. 343-345.
"A Hierarchical Routing System for VLSIs Including Large Macros" by Hinatashi et al., IEEE 1986 Custom Integrated Circuits Conference, May 12-15, 1986, pp. 285-288.
"Rectilinear Area Routing: A Channel Router Approach" by Hudson et al., IEEE ICCD 1985, pp. 468-471.
"IC Mask Layout With A Single Conductor Layer", Akers et al., IEEE 1970, pp. 7-16.
"A Parallel Processing Approach for Logic Module Placement" by Ueda et al., IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 1, Jan. 1983, pp. 39-47.
"A Placement Algorithm for Array Processors" by Chyan et al., IEEE 20th Design Automation Conference, 1983, pp. 182-188.
"Algorithmic Aspects of One-Dimensional Layout Compaction" by Doenhardt et al., IEEE Trans. On Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, pp. 863-878.
"Globally Optimum Compaction of Layout Hierarchies" by D. Marple, 1990 preprint of document A Hierarchy Preserving Hierarchical Compactor.
"A Hierarchical Compactor"by D. Marple, 27th ACM/IEEE Design Automation Conference, 1990, pp. 375-381/
"An Algorithm to Compact a VLSI Symbolic Layout With Mixed Constraints" by Liao et al., IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, No. 2, Apr. 1983, pp. 62-69.
"Physical Design Automation of VLSI Systems" Edited by B. T. Preas et al., Benjamin/Cummings Publishing Company, Chapter 6, pp. 211-267 and 274-281.
"Symbolic Layout Compaction Review" by D. C. Boyer, 25th ACM/IEEE Design Automation Conference, 1988, pp. 383-389.
"Datapath Generator Based on Gate-Level Symbolic Layout", Matsumoto et al., Proc. 27th ACM/IEEE Design Automation Conference, pp. 383-388, 1990.
Matsumoto Nobu
Mori Shojiro
Kabushiki Kaisha Toshiba
Trans Vincent N.
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