Method of and apparatus for discriminating NaN

Details Method of and apparatus for discriminating NaN Method of and apparatus for discriminating NaN

1994-06-17

1996-01-02

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

054814898

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates generally to a floating-point arithmetic employed for processing scientific technology calculations through a data processor and, more particularly, to a technology of discriminating NaN (Not-a-Number) from floating-point numbers. The present invention relates specifically to a method of and an apparatus for discriminating NaN in the binary floating-point numbers based on the IEEE form in which NaN is defined. The present invention relates further to a floating-point register using the NaN discriminating method.


BACKGROUND ART

A scientific technology calculation is one of computer-assisted fields. A floating-point arithmetic is an important function in the scientific technology calculation. One of floating-point number representations in the computer is a representation for binary floating-point numbers according to the IEEE form (a representation for floating-point numbers based on the binary floating-point number representation form established by the IEEE, i.e., Institute of Electrical and Electronic Engineers). "NaN" exclusive of a numeric value is defined in the binary floating-point number based on the IEEE form. NaN is treated differently from the numeric value, and therefore a floating-point number processor requires a detection of NaN.
A floating-point number representation in the IEEE form is a representation based on a bit structure generally having a sign bit, exponent bits and fraction bits. This floating-point number representation is classified into the following forms.
A single precision floating-point number in the IEEE form has, as illustrated in FIG. 38, a 1-bit sign part s indicating positive
egative signs, an 8-bit exponent part e indicating a bias exponent in an exponent representation, a 23-bit fraction part f indicating a fraction in the exponent representation and an undefined area. The single precision floating-point number is substantially expressed in 32 bits, i.e., 4 bytes.
In this case, the bit structure goes as follows:


______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent value 0 Bias exponent 1-254 Maximum exponent value 255 Bias value 127 Decimal point position Most significant integer L e = 0 L = 0 0 < e < 255 L = 1 e = 255 L = 0 Fraction f ______________________________________
A double precision number in the IEEE form has, as shown in FIG. 39, a 1-bit sign part s, a 11-bit exponent part e and a 52-bit fraction part f. The double precision floating-point number is expressed in 64 bits, i.e., 8 bytes.
In this case, a bit structure goes as follows:


______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent value 0 Bias exponent 1-2046 Maximum exponent value 2047 Bias value 1023 Decimal point position Most significant integer L e = 0 L = 0 0 < e < 2047 L = 1 e = 2047 L = 0 Fraction f ______________________________________
An extended double precision floating-point number in the IEEE form has, as illustrated in FIG. 40, a 1-bit sign part s, a 15-bit exponent part e, a 64-bit fraction part f and an undefined area (48 bits).
In this case, a bit structure goes as follows:


______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent 0 value Bias exponent 1-32766 Maximum exponent 32767 value Bias value 16383 Decimal point position Most significant integer L e = 0 L = 0, 1 0 < e < 32767 L = 0, 1 e = 32767 L = unsigni- ficant Fraction f ______________________________________
Supposing that the numeric values are normalized (the most significant bit of the fraction part takes a form of "1"), a value of the floating-point number is expressed in the following representation formula.
By the way, "NAN" is defined in the IEEE form to distinguish normal values fr

REFERENCES:
patent: 4847802 (1989-07-01), Ashton
patent: 5045993 (1991-09-01), Murakami et al.
patent: 5201056 (1993-04-01), Daniel et al.
patent: 5268855 (1993-12-01), Mason et al.

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